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F-StuckmannF-Stuckmann
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[AIE2P] remove ASSERT_[S/Z]EXT in VExtrBcst pattern
Perform the Removal in the postlegalizer custom combiner
1 parent cb7c56c commit 58db43e

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5 files changed

+91
-9
lines changed

5 files changed

+91
-9
lines changed

‎llvm/lib/Target/AIE/AIECombine.td‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,12 @@ def combine_extract_vector_elt_and_zsa_ext : GICombineRule<
5050
(apply [{ applyExtractVecEltAndExt(*${root}, MRI, B, ${matchinfo}); }])
5151
>;
5252

53+
def combine_extract_vector_assert_combine : GICombineRule<
54+
(defs root:$root, build_fn_matchinfo:$matchinfo),
55+
(match (wip_match_opcode G_AIE_ZEXT_EXTRACT_VECTOR_ELT, G_AIE_SEXT_EXTRACT_VECTOR_ELT): $root,
56+
[{ return matchExtractVecEltAssertBcst(*${root}, MRI, (const AIEBaseInstrInfo &)B.getTII(), Observer, ${matchinfo}); }]),
57+
(apply [{ Helper.applyBuildFnNoErase(*${root}, ${matchinfo}); }])>;
58+
5359
def combine_symmetric_build_vector : GICombineRule<
5460
(defs root:$root, build_fn_matchinfo:$matchinfo),
5561
(match (wip_match_opcode G_BUILD_VECTOR): $root,
@@ -392,7 +398,9 @@ def AIE2PostLegalizerCustomCombiner
392398
}
393399

394400
def AIE2PPostLegalizerCustomCombiner
395-
: GICombiner<"AIE2PPostLegalizerCustomCombinerImpl", [ combine_global_load_store_increment,
401+
: GICombiner<"AIE2PPostLegalizerCustomCombinerImpl", [
402+
combine_extract_vector_assert_combine,
403+
combine_global_load_store_increment,
396404
combine_load_store_increment,
397405
ptr_add_immed_chain,
398406
combine_offset_load_store_ptradd,

‎llvm/lib/Target/AIE/AIECombinerHelper.cpp‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4220,3 +4220,74 @@ bool llvm::matchSequentialStores(GStore &StMI, MachineRegisterInfo &MRI,
42204220

42214221
return true;
42224222
}
4223+
4224+
namespace {
4225+
MachineInstr *getBcstFeedByAssertExtVecExtr(MachineInstr &MI,
4226+
MachineRegisterInfo &MRI,
4227+
const AIEBaseInstrInfo &TII) {
4228+
assert(MI.getOpcode() == TII.getGenericExtractVectorEltOpcode(false) ||
4229+
MI.getOpcode() == TII.getGenericExtractVectorEltOpcode(true));
4230+
4231+
/// Get single NonDebug User of \p MI with the opcode \p UseMIOpcode
4232+
auto GetSingleNonDbgUser = [&MRI](MachineInstr &MI,
4233+
unsigned UseMIOpcode) -> MachineInstr * {
4234+
const Register Dst = MI.getOperand(0).getReg();
4235+
if (!MRI.hasOneNonDBGUse(Dst))
4236+
// No convexity due to multiple users, skip.
4237+
return nullptr;
4238+
4239+
MachineInstr *UserMI = &*MRI.use_nodbg_instructions(Dst).begin();
4240+
if (UserMI->getOpcode() != UseMIOpcode)
4241+
return nullptr; // Did not match Opcode, skip.
4242+
4243+
// Found single non debug user with matching opcode.
4244+
return UserMI;
4245+
};
4246+
4247+
// Find G_ASSERT_[S/Z]EXT
4248+
MachineInstr *AnyExtMI = nullptr;
4249+
AnyExtMI = GetSingleNonDbgUser(MI, TargetOpcode::G_ASSERT_SEXT);
4250+
if (!AnyExtMI)
4251+
AnyExtMI = GetSingleNonDbgUser(MI, TargetOpcode::G_ASSERT_ZEXT);
4252+
4253+
if (!AnyExtMI)
4254+
// Could not find G_ASSERT_[S/Z]EXT
4255+
return nullptr;
4256+
4257+
MachineInstr *BcstMI =
4258+
GetSingleNonDbgUser(*AnyExtMI, TII.getGenericBroadcastVectorOpcode());
4259+
return BcstMI;
4260+
}
4261+
} // namespace
4262+
4263+
bool llvm::matchExtractVecEltAssertBcst(MachineInstr &MI,
4264+
MachineRegisterInfo &MRI,
4265+
const AIEBaseInstrInfo &TII,
4266+
GISelChangeObserver &Observer,
4267+
BuildFnTy &MatchInfo) {
4268+
assert((MI.getOpcode() == TII.getGenericExtractVectorEltOpcode(false) ||
4269+
MI.getOpcode() == TII.getGenericExtractVectorEltOpcode(true)) &&
4270+
"Expected a extract_vector_elt");
4271+
const MachineInstr *BcstMI = getBcstFeedByAssertExtVecExtr(MI, MRI, TII);
4272+
if (!BcstMI)
4273+
return false;
4274+
4275+
MatchInfo = [=, &MI, &MRI, &Observer](MachineIRBuilder &B) {
4276+
MachineInstr &AssertExt =
4277+
*MRI.use_nodbg_instructions(MI.getOperand(0).getReg()).begin();
4278+
4279+
MachineOperand &VextrDstMO = MI.getOperand(0);
4280+
Register AssertDst = AssertExt.getOperand(0).getReg();
4281+
4282+
// Skip G_ASSERT_[S/Z]EXT
4283+
Observer.changingInstr(MI);
4284+
VextrDstMO.setReg(AssertDst);
4285+
Observer.changedInstr(MI);
4286+
4287+
// Remove G_ASSERT_[S/Z]EXT
4288+
Observer.erasingInstr(AssertExt);
4289+
AssertExt.removeFromParent();
4290+
};
4291+
4292+
return true;
4293+
}

‎llvm/lib/Target/AIE/AIECombinerHelper.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -303,6 +303,11 @@ bool matchSequentialStores(GStore &MI, MachineRegisterInfo &MRI,
303303
bool matchNarrowTruncLoad(MachineInstr &Phi, MachineRegisterInfo &MRI,
304304
CombinerHelper &Helper, GISelChangeObserver &Observer,
305305
BuildFnTy &MatchInfo);
306+
307+
bool matchExtractVecEltAssertBcst(MachineInstr &MI, MachineRegisterInfo &MRI,
308+
const AIEBaseInstrInfo &TII,
309+
GISelChangeObserver &Observer,
310+
BuildFnTy &MatchInfo);
306311
} // namespace llvm
307312

308313
#endif

‎llvm/test/CodeGen/AIE/aie2p/GlobalIsel/combine-extr-assert-bcst.mir‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,7 @@ body: |
2424
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
2525
; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF [[COPY]](<16 x s16>)
2626
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<32 x s16>), [[C]](s32)
27-
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[AIE_SEXT_EXTRACT_VECTOR_ELT]], 16
28-
; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_SEXT]](s32)
27+
; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[AIE_SEXT_EXTRACT_VECTOR_ELT]](s32)
2928
; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_AIE_UNPAD_VECTOR [[AIE_BROADCAST_VECTOR]](<32 x s16>)
3029
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_UNPAD_VECTOR]](<16 x s16>)
3130
%0:_(<16 x s16>) = COPY $wl0
@@ -54,8 +53,7 @@ body: |
5453
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
5554
; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF [[COPY]](<16 x s16>)
5655
; CHECK-NEXT: [[AIE_ZEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<32 x s16>), [[C]](s32)
57-
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[AIE_ZEXT_EXTRACT_VECTOR_ELT]], 16
58-
; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_ZEXT]](s32)
56+
; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[AIE_ZEXT_EXTRACT_VECTOR_ELT]](s32)
5957
; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_AIE_UNPAD_VECTOR [[AIE_BROADCAST_VECTOR]](<32 x s16>)
6058
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_UNPAD_VECTOR]](<16 x s16>)
6159
%0:_(<16 x s16>) = COPY $wl0

‎llvm/test/CodeGen/AIE/aie2p/shufflevec.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -234,11 +234,11 @@ entry:
234234
define <16 x i16> @test_shuffle_vector_to_extract_broadcast_s16(<16 x i16> noundef %a, <16 x i16> noundef %b) {
235235
; CHECK-LABEL: test_shuffle_vector_to_extract_broadcast_s16:
236236
; CHECK: // %bb.0: // %entry
237-
; CHECK-NEXT: nopa ; nopb ; nops ; ret lr; nopm ; nopv
238-
; CHECK-NEXT: nopx // Delay Slot 5
239-
; CHECK-NEXT: vextract.16 r0, x2, #2, vaddsign1 // Delay Slot 4
237+
; CHECK-NEXT: ret lr
238+
; CHECK-NEXT: nop // Delay Slot 5
239+
; CHECK-NEXT: nop // Delay Slot 4
240240
; CHECK-NEXT: nop // Delay Slot 3
241-
; CHECK-NEXT: vbcst.16 x0, r0 // Delay Slot 2
241+
; CHECK-NEXT: vextbcst.16 x0, x2, #2 // Delay Slot 2
242242
; CHECK-NEXT: nop // Delay Slot 1
243243
entry:
244244
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>

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