[AIE2P][unittest] add unittest for Vextr G_ASSERT_[S/Z]EXT BCST

Author: F-Stuckmann

llvm/test/CodeGen/AIE/aie2p/GlobalIsel/combine-extr-assert-bcst.mir

@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+#
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
+
+# RUN: llc -mtriple aie2p  -run-pass=aie2p-postlegalizer-custom-combiner -verify-machineinstrs -o - %s  | FileCheck %s
+
+
+---
+name:            extr_assert_sext_bcst
+alignment:       1
+legalized:       true
+body:             |
+  bb.0:
+    liveins: $wl0, $wl1
+
+    ; CHECK-LABEL: name: extr_assert_sext_bcst
+    ; CHECK: liveins: $wl0, $wl1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wl0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF [[COPY]](<16 x s16>)
+    ; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<32 x s16>), [[C]](s32)
+    ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[AIE_SEXT_EXTRACT_VECTOR_ELT]], 16
+    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_SEXT]](s32)
+    ; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_AIE_UNPAD_VECTOR [[AIE_BROADCAST_VECTOR]](<32 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_UNPAD_VECTOR]](<16 x s16>)
+    %0:_(<16 x s16>) = COPY $wl0
+    %3:_(s32) = G_CONSTANT i32 2
+    %10:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF %0(<16 x s16>)
+    %8:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT %10(<32 x s16>), %3(s32)
+    %5:_(s32) = G_ASSERT_SEXT %8, 16
+    %6:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR %5(s32)
+    %2:_(<16 x s16>) = G_AIE_UNPAD_VECTOR %6(<32 x s16>)
+    PseudoRET implicit $lr, implicit %2(<16 x s16>)
+
+...
+
+---
+name:            extr_assert_zext_bcst
+alignment:       1
+legalized:       true
+body:             |
+  bb.0:
+    liveins: $wl0, $wl1
+
+    ; CHECK-LABEL: name: extr_assert_zext_bcst
+    ; CHECK: liveins: $wl0, $wl1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wl0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF [[COPY]](<16 x s16>)
+    ; CHECK-NEXT: [[AIE_ZEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<32 x s16>), [[C]](s32)
+    ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[AIE_ZEXT_EXTRACT_VECTOR_ELT]], 16
+    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_ZEXT]](s32)
+    ; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_AIE_UNPAD_VECTOR [[AIE_BROADCAST_VECTOR]](<32 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_UNPAD_VECTOR]](<16 x s16>)
+    %0:_(<16 x s16>) = COPY $wl0
+    %3:_(s32) = G_CONSTANT i32 2
+    %10:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF %0(<16 x s16>)
+    %8:_(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %10(<32 x s16>), %3(s32)
+    %5:_(s32) = G_ASSERT_ZEXT %8, 16
+    %6:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR %5(s32)
+    %2:_(<16 x s16>) = G_AIE_UNPAD_VECTOR %6(<32 x s16>)
+    PseudoRET implicit $lr, implicit %2(<16 x s16>)
+
+...