Revert "[AIE2P] Do not materalize assertEXT within VEXTBCST pattern"

F-Stuckmann · F-Stuckmann · commit 95f7e9140a87 · 2025-10-16T09:52:29.000-04:00
This reverts commit 8716101.
diff --git a/llvm/lib/Target/AIE/AIECombine.td b/llvm/lib/Target/AIE/AIECombine.td
@@ -42,11 +42,11 @@ def combine_globalval_offset : GICombineRule<
   (apply [{  applyGlobalValOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
 >;
 
-def combine_extract_vector_elt_and_zsa_ext_matchdata: GIDefMatchData<"std::pair<MachineInstr *, std::pair<bool, bool>>">;
+def combine_extract_vector_elt_and_zsa_ext_matchdata: GIDefMatchData<"std::pair<MachineInstr *, bool>">;
 def combine_extract_vector_elt_and_zsa_ext : GICombineRule<
   (defs root:$root, combine_extract_vector_elt_and_zsa_ext_matchdata:$matchinfo),
   (match (wip_match_opcode G_EXTRACT_VECTOR_ELT): $root,
-  [{ return matchExtractVecEltAndExt(*${root}, MRI, (const AIEBaseInstrInfo &)B.getTII(), ${matchinfo}); }]),
+  [{ return matchExtractVecEltAndExt(*${root}, MRI, ${matchinfo}); }]),
   (apply [{ applyExtractVecEltAndExt(*${root}, MRI, B, ${matchinfo}); }])
 >;
 
diff --git a/llvm/lib/Target/AIE/AIECombinerHelper.cpp b/llvm/lib/Target/AIE/AIECombinerHelper.cpp
@@ -1048,56 +1048,33 @@ void llvm::applyGlobalValOffset(MachineInstr &MI, MachineRegisterInfo &MRI,
       B.buildConstant(LLT::scalar(20), -static_cast<int64_t>(Offset)));
 }
 
-namespace {
-bool feedsAnyExtBcstUse(MachineInstr &MI, MachineRegisterInfo &MRI,
-                        const AIEBaseInstrInfo &TII) {
-  assert(MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT);
-
-  auto IsSingleNonDbgUse = [&MRI](MachineInstr &MI,
-                                  unsigned UseMIOpcode) -> MachineInstr * {
-    const Register Dst = MI.getOperand(0).getReg();
-    if (!MRI.hasOneNonDBGUse(Dst))
-      return nullptr;
-
-    MachineInstr *UseMI = &*MRI.use_nodbg_instructions(Dst).begin();
-    if (UseMI->getOpcode() != UseMIOpcode)
-      return nullptr;
-    return UseMI;
-  };
-
-  auto *AnyExtMI = IsSingleNonDbgUse(MI, TargetOpcode::G_ANYEXT);
-  if (!AnyExtMI)
-    return false;
-
-  auto *BcstMI =
-      IsSingleNonDbgUse(*AnyExtMI, TII.getGenericBroadcastVectorOpcode());
-  return BcstMI;
-}
-} // namespace
-
 bool llvm::matchExtractVecEltAndExt(
-    MachineInstr &MI, MachineRegisterInfo &MRI, const AIEBaseInstrInfo &TII,
-    std::pair<MachineInstr *, std::pair<bool, bool>> &MatchInfo) {
+    MachineInstr &MI, MachineRegisterInfo &MRI,
+    std::pair<MachineInstr *, bool> &MatchInfo) {
+
   assert(MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT &&
          "Expected a extract_vector_elt");
   Register DstReg = MI.getOperand(0).getReg();
+  const LLT S8 = LLT::scalar(8);
+  const LLT S16 = LLT::scalar(16);
   LLT SrcVecTy = MRI.getType(MI.getOperand(1).getReg());
   // Extracts from vectors <= 64-bits are lowered to bit-arithmetic in
   // legalization
   if (SrcVecTy.getSizeInBits() <= 64)
     return false;
+  LLT SrcEltTy = SrcVecTy.getElementType();
+  if (SrcEltTy != S8 && SrcEltTy != S16)
+    return false;
   if (!MRI.hasOneNonDBGUse(DstReg))
     return false;
-
-  const bool BuildAssert = !feedsAnyExtBcstUse(MI, MRI, TII);
   MachineInstr *ExtMI = &*MRI.use_instr_nodbg_begin(DstReg);
   switch (ExtMI->getOpcode()) {
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_SEXT:
-    MatchInfo = std::make_pair(ExtMI, std::make_pair(/*SEXT=*/1, BuildAssert));
+    MatchInfo = std::make_pair(ExtMI, 1);
     return true;
   case TargetOpcode::G_ZEXT:
-    MatchInfo = std::make_pair(ExtMI, std::make_pair(/*SEXT=*/0, BuildAssert));
+    MatchInfo = std::make_pair(ExtMI, 0);
     return true;
   default:
     return false;
@@ -1107,11 +1084,9 @@ bool llvm::matchExtractVecEltAndExt(
 
 void llvm::applyExtractVecEltAndExt(
     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
-    std::pair<MachineInstr *, std::pair<bool, bool>> &MatchInfo) {
+    std::pair<MachineInstr *, bool> &MatchInfo) {
   B.setInstrAndDebugLoc(MI);
-  auto [MatchMI, BoolPair] = MatchInfo;
-  auto [IsSignedExt, BuildAssert] = BoolPair;
-
+  auto [MatchMI, IsSignedExt] = MatchInfo;
   const Register ExtractDstReg = MI.getOperand(0).getReg();
   const LLT ExtractDstTy = MRI.getType(ExtractDstReg);
   const Register ExtendDstReg = MatchMI->getOperand(0).getReg();
@@ -1122,23 +1097,19 @@ void llvm::applyExtractVecEltAndExt(
   const AIEBaseInstrInfo &AIETII = (const AIEBaseInstrInfo &)B.getTII();
   const unsigned Opcode =
       AIETII.getGenericExtractVectorEltOpcode(/*sign ext*/ IsSignedExt);
-
-  const Register ExtractElt32BitDst =
-      BuildAssert ? MRI.createGenericVirtualRegister(S32) : ExtendDstReg;
+  const Register ExtractElt32BitDst = MRI.createGenericVirtualRegister(S32);
   B.buildInstr(Opcode, {ExtractElt32BitDst}, {SrcReg0, SrcReg1});
 
-  if (BuildAssert) {
-    const unsigned AssertOpcode =
-        IsSignedExt ? TargetOpcode::G_ASSERT_SEXT : TargetOpcode::G_ASSERT_ZEXT;
-    if (ExtendDstTy == LLT::scalar(32)) {
-      B.buildAssertInstr(AssertOpcode, ExtendDstReg, ExtractElt32BitDst,
-                         ExtractDstTy.getSizeInBits());
-    } else {
-      const Register Assert32BitDst = MRI.createGenericVirtualRegister(S32);
-      B.buildAssertInstr(AssertOpcode, Assert32BitDst, ExtractElt32BitDst,
-                         ExtractDstTy.getSizeInBits());
-      B.buildExtOrTrunc(MatchMI->getOpcode(), ExtendDstReg, Assert32BitDst);
-    }
+  const unsigned AssertOpcode =
+      IsSignedExt ? TargetOpcode::G_ASSERT_SEXT : TargetOpcode::G_ASSERT_ZEXT;
+  if (ExtendDstTy == LLT::scalar(32)) {
+    B.buildAssertInstr(AssertOpcode, ExtendDstReg, ExtractElt32BitDst,
+                       ExtractDstTy.getSizeInBits());
+  } else {
+    const Register Assert32BitDst = MRI.createGenericVirtualRegister(S32);
+    B.buildAssertInstr(AssertOpcode, Assert32BitDst, ExtractElt32BitDst,
+                       ExtractDstTy.getSizeInBits());
+    B.buildExtOrTrunc(MatchMI->getOpcode(), ExtendDstReg, Assert32BitDst);
   }
 
   MI.eraseFromParent();
diff --git a/llvm/lib/Target/AIE/AIECombinerHelper.h b/llvm/lib/Target/AIE/AIECombinerHelper.h
@@ -156,12 +156,11 @@ bool canAdvanceOp(MachineInstr &MemI, MachineInstr &Dest,
 MachineInstr *getDefIgnoringCopiesAndBitcasts(Register Reg,
                                               const MachineRegisterInfo &MRI);
 
-bool matchExtractVecEltAndExt(
-    MachineInstr &MI, MachineRegisterInfo &MRI, const AIEBaseInstrInfo &TII,
-    std::pair<MachineInstr *, std::pair<bool, bool>> &MatchInfo);
-void applyExtractVecEltAndExt(
-    MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
-    std::pair<MachineInstr *, std::pair<bool, bool>> &MatchInfo);
+bool matchExtractVecEltAndExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+                              std::pair<MachineInstr *, bool> &MatchInfo);
+void applyExtractVecEltAndExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+                              MachineIRBuilder &B,
+                              std::pair<MachineInstr *, bool> &MatchInfo);
 
 bool matchSplatVector(MachineInstr &MI, MachineRegisterInfo &MRI,
                       std::pair<Register, Register> &MatchInfo);
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/prelegalizercombiner-shuffle-vector.mir b/llvm/test/CodeGen/AIE/GlobalISel/prelegalizercombiner-shuffle-vector.mir
@@ -445,7 +445,8 @@ body:             |
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
     ; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<32 x s16>) = G_AIE_PAD_VECTOR_UNDEF [[COPY]](<16 x s16>)
     ; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<32 x s16>), [[C]](s32)
-    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[AIE_SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[AIE_SEXT_EXTRACT_VECTOR_ELT]], 16
+    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_SEXT]](s32)
     ; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_AIE_UNPAD_VECTOR [[AIE_BROADCAST_VECTOR]](<32 x s16>)
     ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_UNPAD_VECTOR]](<16 x s16>)
     %0:_(<16 x s16>) = COPY $wl0
diff --git a/llvm/test/CodeGen/AIE/aie2p/shufflevec.ll b/llvm/test/CodeGen/AIE/aie2p/shufflevec.ll
@@ -234,11 +234,11 @@ entry:
 define <16 x i16> @test_shuffle_vector_to_extract_broadcast_s16(<16 x i16> noundef %a, <16 x i16> noundef %b) {
 ; CHECK-LABEL: test_shuffle_vector_to_extract_broadcast_s16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ret lr
-; CHECK-NEXT:    nop // Delay Slot 5
-; CHECK-NEXT:    nop // Delay Slot 4
+; CHECK-NEXT:    nopa ; nopb ; nops ; ret lr; nopm ; nopv
+; CHECK-NEXT:    nopx // Delay Slot 5
+; CHECK-NEXT:    vextract.16 r0, x2, #2, vaddsign1 // Delay Slot 4
 ; CHECK-NEXT:    nop // Delay Slot 3
-; CHECK-NEXT:    vextbcst.16 x0, x2, #2 // Delay Slot 2
+; CHECK-NEXT:    vbcst.16 x0, r0 // Delay Slot 2
 ; CHECK-NEXT:    nop // Delay Slot 1
 entry:
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
