[AIEX] do not insert G_ASSERT_[Z/S]EXT after AnyExt

Author: F-Stuckmann

llvm/lib/Target/AIE/AIELegalizerHelper.cpp

@@ -1394,12 +1394,6 @@ bool AIELegalizerHelper::legalizeG_FMUL(LegalizerHelper &Helper,
 
   SrcLHS = MIRBuilder.buildAnyExt(S32, SrcLHS).getReg(0);
   SrcRHS = MIRBuilder.buildAnyExt(S32, SrcRHS).getReg(0);
-  SrcLHS = MIRBuilder
-               .buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, {S32}, SrcLHS, 16)
-               .getReg(0);
-  SrcRHS = MIRBuilder
-               .buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, {S32}, SrcRHS, 16)
-               .getReg(0);
 
   const LLT BroadcastVecLLT = V32BF16;
   const unsigned BroadcastOpc =
@@ -1416,7 +1410,7 @@ bool AIELegalizerHelper::legalizeG_FMUL(LegalizerHelper &Helper,
 
   const Register IdxReg = MIRBuilder.buildConstant(S32, 0).getReg(0);
   const unsigned ExtractEltOpc =
-      ST.getInstrInfo()->getGenericExtractVectorEltOpcode(/*ZeroExt*/ false);
+      ST.getInstrInfo()->getGenericExtractVectorEltOpcode(/*SignExt=*/false);
   Res = MIRBuilder.buildInstr(ExtractEltOpc, {S32}, {Res, IdxReg}).getReg(0);
   Res = MIRBuilder.buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, {S32}, Res, 16)
             .getReg(0);

llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-fmul.mir

@@ -3,7 +3,7 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
 
 # RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 
@@ -17,15 +17,13 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r1
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
-    ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
-    ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
-    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_ZEXT]](s32)
-    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR1:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[ASSERT_ZEXT1]](s32)
+    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[COPY]](s32)
+    ; CHECK-NEXT: [[AIE_BROADCAST_VECTOR1:%[0-9]+]]:_(<32 x s16>) = G_AIE_BROADCAST_VECTOR [[COPY1]](s32)
     ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<32 x s16>) = G_FMUL [[AIE_BROADCAST_VECTOR]], [[AIE_BROADCAST_VECTOR1]]
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK-NEXT: [[AIE_ZEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT [[FMUL]](<32 x s16>), [[C]](s32)
-    ; CHECK-NEXT: [[ASSERT_ZEXT2:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[AIE_ZEXT_EXTRACT_VECTOR_ELT]], 16
-    ; CHECK-NEXT: $r0 = COPY [[ASSERT_ZEXT2]](s32)
+    ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[AIE_ZEXT_EXTRACT_VECTOR_ELT]], 16
+    ; CHECK-NEXT: $r0 = COPY [[ASSERT_ZEXT]](s32)
     ; CHECK-NEXT: PseudoRET implicit $lr, implicit $r0
     %0:_(s32) = COPY $r1
     %1:_(s16) = G_TRUNC %0(s32)