Skip to content

Commit e71a4b2

Browse files
Martien de JongF-Stuckmann
Martien de Jong
authored and
F-Stuckmann
committed
[AIE2P] split offsets before postincrment in large Load/Stores
Put the zero-offset part last, since it doesn't need the pointer to survive.
1 parent d381e47 commit e71a4b2

File tree

8 files changed

+535
-531
lines changed

8 files changed

+535
-531
lines changed

‎llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1985,7 +1985,9 @@ bool AIE2PInstructionSelector::selectWideG_AIE_LOAD_STORE(
19851985
case AIE2P::G_AIE_POSTINC_STORE:
19861986
case AIE2P::G_AIE_POSTINC_2D_STORE:
19871987
case AIE2P::G_AIE_POSTINC_3D_STORE: {
1988-
for (unsigned SubRegIdx = 0; SubRegIdx < SplitFactor; ++SubRegIdx) {
1988+
// Split Offsets first and then perform the postinc.
1989+
// For consistency, also handle G_STORE in the same manner.
1990+
for (int SubRegIdx = SplitFactor - 1; SubRegIdx >= 0; SubRegIdx--) {
19891991
const unsigned Offset = SubRegIdx * 64;
19901992
auto Copy = MIB.buildInstr(TargetOpcode::COPY, {SubRegs[SubRegIdx]}, {})
19911993
.addReg(AMI.SrcDstOp.getReg(), 0,
@@ -2057,7 +2059,9 @@ bool AIE2PInstructionSelector::selectWideG_AIE_LOAD_STORE(
20572059
case AIE2P::G_AIE_POSTINC_LOAD:
20582060
case AIE2P::G_AIE_POSTINC_2D_LOAD:
20592061
case AIE2P::G_AIE_POSTINC_3D_LOAD: {
2060-
for (unsigned SubRegIdx = 0; SubRegIdx < SplitFactor; ++SubRegIdx) {
2062+
// Split Offsets first and then perform the postinc.
2063+
// For consistency, also handle G_LOAD in the same manner.
2064+
for (int SubRegIdx = SplitFactor - 1; SubRegIdx >= 0; SubRegIdx--) {
20612065
MachineInstrBuilder Load;
20622066
if (SubRegIdx == 0) {
20632067
Load = MIB.buildInstr(LSO.ISelOpcode, {SubRegs[0]}, {});

‎llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-vector-load.mir‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# See https://llvm.org/LICENSE.txt for license information.
55
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
66
#
7-
# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
7+
# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
88
# RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
99

1010
---
@@ -217,9 +217,9 @@ body: |
217217
; CHECK: liveins: $p0
218218
; CHECK-NEXT: {{ $}}
219219
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
220-
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 0 :: (load (<16 x s32>), align 128)
221-
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm1:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 64 :: (load (<16 x s32>) from unknown-address + 64)
222-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:fifo1024 = REG_SEQUENCE [[VLDA_dmx_lda_fifohl_idx_imm]], %subreg.sub_lo_fifo, [[VLDA_dmx_lda_fifohl_idx_imm1]], %subreg.sub_hi_fifo
220+
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 64 :: (load (<16 x s32>), align 128)
221+
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm1:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 0 :: (load (<16 x s32>) from unknown-address + 64)
222+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:fifo1024 = REG_SEQUENCE [[VLDA_dmx_lda_fifohl_idx_imm1]], %subreg.sub_lo_fifo, [[VLDA_dmx_lda_fifohl_idx_imm]], %subreg.sub_hi_fifo
223223
; CHECK-NEXT: $lf0 = COPY [[REG_SEQUENCE]]
224224
%1:ptrregbank(p0) = COPY $p0
225225
%0:fiforegbank(<32 x s32>) = G_LOAD %1(p0) :: (load (<32 x s32>))
@@ -238,9 +238,9 @@ body: |
238238
; CHECK: liveins: $p0
239239
; CHECK-NEXT: {{ $}}
240240
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
241-
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 0 :: (load (<32 x s16>), align 128)
242-
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm1:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 64 :: (load (<32 x s16>) from unknown-address + 64)
243-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:fifo1024 = REG_SEQUENCE [[VLDA_dmx_lda_fifohl_idx_imm]], %subreg.sub_lo_fifo, [[VLDA_dmx_lda_fifohl_idx_imm1]], %subreg.sub_hi_fifo
241+
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 64 :: (load (<32 x s16>), align 128)
242+
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm1:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 0 :: (load (<32 x s16>) from unknown-address + 64)
243+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:fifo1024 = REG_SEQUENCE [[VLDA_dmx_lda_fifohl_idx_imm1]], %subreg.sub_lo_fifo, [[VLDA_dmx_lda_fifohl_idx_imm]], %subreg.sub_hi_fifo
244244
; CHECK-NEXT: $lf0 = COPY [[REG_SEQUENCE]]
245245
%1:ptrregbank(p0) = COPY $p0
246246
%0:fiforegbank(<64 x s16>) = G_LOAD %1(p0) :: (load (<64 x s16>))
@@ -258,9 +258,9 @@ body: |
258258
; CHECK: liveins: $p0
259259
; CHECK-NEXT: {{ $}}
260260
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
261-
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 0 :: (load (<64 x s8>), align 128)
262-
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm1:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 64 :: (load (<64 x s8>) from unknown-address + 64)
263-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:fifo1024 = REG_SEQUENCE [[VLDA_dmx_lda_fifohl_idx_imm]], %subreg.sub_lo_fifo, [[VLDA_dmx_lda_fifohl_idx_imm1]], %subreg.sub_hi_fifo
261+
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 64 :: (load (<64 x s8>), align 128)
262+
; CHECK-NEXT: [[VLDA_dmx_lda_fifohl_idx_imm1:%[0-9]+]]:fifo512 = VLDA_dmx_lda_fifohl_idx_imm [[COPY]], 0 :: (load (<64 x s8>) from unknown-address + 64)
263+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:fifo1024 = REG_SEQUENCE [[VLDA_dmx_lda_fifohl_idx_imm1]], %subreg.sub_lo_fifo, [[VLDA_dmx_lda_fifohl_idx_imm]], %subreg.sub_hi_fifo
264264
; CHECK-NEXT: $lf0 = COPY [[REG_SEQUENCE]]
265265
%1:ptrregbank(p0) = COPY $p0
266266
%0:fiforegbank(<128 x s8>) = G_LOAD %1(p0) :: (load (<128 x s8>))
@@ -278,9 +278,9 @@ body: |
278278
; CHECK: liveins: $p0
279279
; CHECK-NEXT: {{ $}}
280280
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
281-
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 0 :: (load (<32 x s16>), align 128)
282-
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo1:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 64 :: (load (<32 x s16>) from unknown-address + 64)
283-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VLD_x_idx_imm_pseudo]], %subreg.sub_512_lo, [[VLD_x_idx_imm_pseudo1]], %subreg.sub_512_hi
281+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 64 :: (load (<32 x s16>), align 128)
282+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo1:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 0 :: (load (<32 x s16>) from unknown-address + 64)
283+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VLD_x_idx_imm_pseudo1]], %subreg.sub_512_lo, [[VLD_x_idx_imm_pseudo]], %subreg.sub_512_hi
284284
; CHECK-NEXT: $y0 = COPY [[REG_SEQUENCE]]
285285
%1:ptrregbank(p0) = COPY $p0
286286
%0:vregbank(<64 x s16>) = G_LOAD %1(p0) :: (load (<64 x s16>))
@@ -298,9 +298,9 @@ body: |
298298
; CHECK: liveins: $p0
299299
; CHECK-NEXT: {{ $}}
300300
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
301-
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 0 :: (load (<16 x s32>), align 128)
302-
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo1:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 64 :: (load (<16 x s32>) from unknown-address + 64)
303-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VLD_x_idx_imm_pseudo]], %subreg.sub_512_lo, [[VLD_x_idx_imm_pseudo1]], %subreg.sub_512_hi
301+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 64 :: (load (<16 x s32>), align 128)
302+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo1:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 0 :: (load (<16 x s32>) from unknown-address + 64)
303+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VLD_x_idx_imm_pseudo1]], %subreg.sub_512_lo, [[VLD_x_idx_imm_pseudo]], %subreg.sub_512_hi
304304
; CHECK-NEXT: $y0 = COPY [[REG_SEQUENCE]]
305305
%1:ptrregbank(p0) = COPY $p0
306306
%0:vregbank(<32 x s32>) = G_LOAD %1(p0) :: (load (<32 x s32>))
@@ -318,9 +318,9 @@ body: |
318318
; CHECK: liveins: $p0
319319
; CHECK-NEXT: {{ $}}
320320
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
321-
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 0 :: (load (<64 x s8>), align 128)
322-
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo1:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 64 :: (load (<64 x s8>) from unknown-address + 64)
323-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VLD_x_idx_imm_pseudo]], %subreg.sub_512_lo, [[VLD_x_idx_imm_pseudo1]], %subreg.sub_512_hi
321+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 64 :: (load (<64 x s8>), align 128)
322+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo1:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo [[COPY]], 0 :: (load (<64 x s8>) from unknown-address + 64)
323+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VLD_x_idx_imm_pseudo1]], %subreg.sub_512_lo, [[VLD_x_idx_imm_pseudo]], %subreg.sub_512_hi
324324
; CHECK-NEXT: $y0 = COPY [[REG_SEQUENCE]]
325325
%1:ptrregbank(p0) = COPY $p0
326326
%0:vregbank(<128 x s8>) = G_LOAD %1(p0) :: (load (<128 x s8>))
@@ -338,9 +338,9 @@ body: |
338338
; CHECK: liveins: $p0
339339
; CHECK-NEXT: {{ $}}
340340
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
341-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<16 x s32>), align 128)
342-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<16 x s32>) from unknown-address + 64)
343-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc1024 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_512_acc_hi
341+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<16 x s32>), align 128)
342+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<16 x s32>) from unknown-address + 64)
343+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc1024 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_512_acc_hi
344344
; CHECK-NEXT: $cml0 = COPY [[REG_SEQUENCE]]
345345
%1:ptrregbank(p0) = COPY $p0
346346
%0:accregbank(<32 x s32>) = G_LOAD %1(p0) :: (load (<32 x s32>))
@@ -358,9 +358,9 @@ body: |
358358
; CHECK: liveins: $p0
359359
; CHECK-NEXT: {{ $}}
360360
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
361-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<8 x s64>), align 128)
362-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<8 x s64>) from unknown-address + 64)
363-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc1024 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_512_acc_hi
361+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<8 x s64>), align 128)
362+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<8 x s64>) from unknown-address + 64)
363+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc1024 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_512_acc_hi
364364
; CHECK-NEXT: $cml0 = COPY [[REG_SEQUENCE]]
365365
%1:ptrregbank(p0) = COPY $p0
366366
%0:accregbank(<16 x s64>) = G_LOAD %1(p0) :: (load (<16 x s64>))
@@ -378,11 +378,11 @@ body: |
378378
; CHECK: liveins: $p0
379379
; CHECK-NEXT: {{ $}}
380380
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
381-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<16 x s32>), align 256)
382-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<16 x s32>) from unknown-address + 64)
383-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm2:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 128 :: (load (<16 x s32>) from unknown-address + 128, align 128)
384-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm3:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 192 :: (load (<16 x s32>) from unknown-address + 192)
385-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc2048 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_512_acc_hi, [[VLDA_dmx_lda_bm_idx_imm2]], %subreg.sub_1024_acc_hi_then_sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm3]], %subreg.sub_1024_acc_hi_then_sub_512_acc_hi
381+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 192 :: (load (<16 x s32>), align 256)
382+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 128 :: (load (<16 x s32>) from unknown-address + 64)
383+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm2:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<16 x s32>) from unknown-address + 128, align 128)
384+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm3:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<16 x s32>) from unknown-address + 192)
385+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc2048 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm3]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm2]], %subreg.sub_512_acc_hi, [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_1024_acc_hi_then_sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_1024_acc_hi_then_sub_512_acc_hi
386386
; CHECK-NEXT: $dm0 = COPY [[REG_SEQUENCE]]
387387
%1:ptrregbank(p0) = COPY $p0
388388
%0:accregbank(<64 x s32>) = G_LOAD %1(p0) :: (load (<64 x s32>))
@@ -400,11 +400,11 @@ body: |
400400
; CHECK: liveins: $p0
401401
; CHECK-NEXT: {{ $}}
402402
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
403-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<8 x s64>), align 256)
404-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<8 x s64>) from unknown-address + 64)
405-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm2:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 128 :: (load (<8 x s64>) from unknown-address + 128, align 128)
406-
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm3:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 192 :: (load (<8 x s64>) from unknown-address + 192)
407-
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc2048 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_512_acc_hi, [[VLDA_dmx_lda_bm_idx_imm2]], %subreg.sub_1024_acc_hi_then_sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm3]], %subreg.sub_1024_acc_hi_then_sub_512_acc_hi
403+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 192 :: (load (<8 x s64>), align 256)
404+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm1:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 128 :: (load (<8 x s64>) from unknown-address + 64)
405+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm2:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 64 :: (load (<8 x s64>) from unknown-address + 128, align 128)
406+
; CHECK-NEXT: [[VLDA_dmx_lda_bm_idx_imm3:%[0-9]+]]:acc512 = VLDA_dmx_lda_bm_idx_imm [[COPY]], 0 :: (load (<8 x s64>) from unknown-address + 192)
407+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc2048 = REG_SEQUENCE [[VLDA_dmx_lda_bm_idx_imm3]], %subreg.sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm2]], %subreg.sub_512_acc_hi, [[VLDA_dmx_lda_bm_idx_imm1]], %subreg.sub_1024_acc_hi_then_sub_512_acc_lo, [[VLDA_dmx_lda_bm_idx_imm]], %subreg.sub_1024_acc_hi_then_sub_512_acc_hi
408408
; CHECK-NEXT: $dm0 = COPY [[REG_SEQUENCE]]
409409
%1:ptrregbank(p0) = COPY $p0
410410
%0:accregbank(<32 x s64>) = G_LOAD %1(p0) :: (load (<32 x s64>))

0 commit comments

Comments
 (0)