[AIEX] Extend Staged 2D/3D regalloc to avoid spills #685
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| //===-- AIEUnallocatedSuperRegRewriter.cpp - Constrain tied sub-registers -===// | ||
| // | ||
| // This file is licensed under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| // (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
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| #include "AIEBaseInstrInfo.h" | ||
| #include "AIEBaseRegisterInfo.h" | ||
| #include "AIESuperRegUtils.h" | ||
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| #include "llvm/ADT/MapVector.h" | ||
| #include "llvm/ADT/SmallSet.h" | ||
| #include "llvm/CodeGen/LiveDebugVariables.h" | ||
| #include "llvm/CodeGen/LiveIntervals.h" | ||
| #include "llvm/CodeGen/LiveRegMatrix.h" | ||
| #include "llvm/CodeGen/LiveStacks.h" | ||
| #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" | ||
| #include "llvm/CodeGen/MachineFunction.h" | ||
| #include "llvm/CodeGen/MachineFunctionPass.h" | ||
| #include "llvm/CodeGen/MachineInstr.h" | ||
| #include "llvm/CodeGen/MachineInstrBuilder.h" | ||
| #include "llvm/CodeGen/MachineOperand.h" | ||
| #include "llvm/CodeGen/MachineRegisterInfo.h" | ||
| #include "llvm/CodeGen/Passes.h" | ||
| #include "llvm/CodeGen/SlotIndexes.h" | ||
| #include "llvm/CodeGen/TargetInstrInfo.h" | ||
| #include "llvm/CodeGen/TargetSubtargetInfo.h" | ||
| #include "llvm/CodeGen/VirtRegMap.h" | ||
| #include "llvm/Support/Debug.h" | ||
| #include "llvm/Support/raw_ostream.h" | ||
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| using namespace llvm; | ||
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| #define DEBUG_TYPE "aie-ra-prepare" | ||
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| namespace { | ||
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| using RegRewriteInfo = std::vector<std::pair<Register, SmallSet<int, 8>>>; | ||
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| /// Split large unallocated compound registers into multiple new smaller vregs | ||
| /// Than can be allocated to scalar registers. | ||
| class AIEUnallocatedSuperRegRewriter : public MachineFunctionPass { | ||
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| public: | ||
| static char ID; | ||
| AIEUnallocatedSuperRegRewriter() : MachineFunctionPass(ID) {} | ||
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| void getAnalysisUsage(AnalysisUsage &AU) const override { | ||
| AU.setPreservesCFG(); | ||
| AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>(); | ||
| AU.addRequired<VirtRegMapWrapperLegacy>(); | ||
| AU.addPreserved<VirtRegMapWrapperLegacy>(); | ||
| AU.addRequired<SlotIndexesWrapperPass>(); | ||
| AU.addPreserved<SlotIndexesWrapperPass>(); | ||
| AU.addRequired<LiveDebugVariablesWrapperLegacy>(); | ||
| AU.addPreserved<LiveDebugVariablesWrapperLegacy>(); | ||
| AU.addRequired<LiveStacksWrapperLegacy>(); | ||
| AU.addPreserved<LiveStacksWrapperLegacy>(); | ||
| AU.addRequired<LiveIntervalsWrapperPass>(); | ||
| AU.addPreserved<LiveIntervalsWrapperPass>(); | ||
| AU.addRequired<LiveRegMatrixWrapperLegacy>(); | ||
| AU.addPreserved<LiveRegMatrixWrapperLegacy>(); | ||
| MachineFunctionPass::getAnalysisUsage(AU); | ||
| } | ||
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| bool runOnMachineFunction(MachineFunction &Fn) override; | ||
| }; | ||
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| /// Identify unallocated virtual registers that can be split into subregisters. | ||
| /// Returns a list of candidate registers with their rewritable subregister | ||
| /// indices, excluding unused registers and those already assigned to physical | ||
| /// registers. | ||
| static RegRewriteInfo getRewriteCandidates(MachineRegisterInfo &MRI, | ||
| const AIEBaseRegisterInfo &TRI, | ||
| VirtRegMap &VRM) { | ||
| RegRewriteInfo RegistersToRewrite; | ||
| for (unsigned VRegIdx = 0, End = MRI.getNumVirtRegs(); VRegIdx != End; | ||
| ++VRegIdx) { | ||
| const Register Reg = Register::index2VirtReg(VRegIdx); | ||
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| // Ignore un-used registers | ||
|
Collaborator
Author
There was a problem hiding this comment. Complete the comment. |
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| if (MRI.reg_nodbg_empty(Reg) || VRM.hasPhys(Reg)) | ||
| continue; | ||
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| SmallSet<int, 8> RewritableSubRegs = | ||
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| AIESuperRegUtils::getRewritableSubRegs(Reg, MRI, TRI); | ||
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| if (RewritableSubRegs.empty()) | ||
| continue; | ||
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| LLVM_DEBUG(dbgs() << "Candidate " << printReg(Reg, &TRI, 0, &MRI) << ":" | ||
| << printRegClassOrBank(Reg, MRI, &TRI) << '\n'); | ||
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| RegistersToRewrite.push_back({Reg, RewritableSubRegs}); | ||
| } | ||
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| LLVM_DEBUG(dbgs() << "Found " << RegistersToRewrite.size() | ||
| << " candidate register(s) for rewriting\n"); | ||
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| return RegistersToRewrite; | ||
| } | ||
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| /// Split candidate registers into independent virtual registers for each | ||
| /// subregister. Each composite register is rewritten using its subregister | ||
| /// indices, with live intervals and debug information updated accordingly. | ||
| void rewriteCandidates(RegRewriteInfo &RegistersToRewrite, | ||
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Collaborator
There was a problem hiding this comment. Are these the candidates to rewrite? |
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| MachineRegisterInfo &MRI, const AIEBaseRegisterInfo &TRI, | ||
| VirtRegMap &VRM, LiveRegMatrix &LRM, LiveIntervals &LIS, | ||
| SlotIndexes &Indexes, LiveDebugVariables &DebugVars) { | ||
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| LLVM_DEBUG(dbgs() << "Rewriting " << RegistersToRewrite.size() | ||
| << " candidate register(s)\n"); | ||
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| for (auto [VReg, SubRegs] : RegistersToRewrite) { | ||
| LLVM_DEBUG(dbgs() << " Rewriting " << printReg(VReg, &TRI, 0, &MRI) | ||
| << " into " << SubRegs.size() << " subregister(s)\n"); | ||
| AIESuperRegUtils::rewriteSuperReg( | ||
| VReg, /*std::optional<Register> AssignedPhysReg = */ {}, SubRegs, MRI, | ||
|
Collaborator
Author
There was a problem hiding this comment. Local var for Assign... |
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| TRI, VRM, LRM, LIS, Indexes, DebugVars); | ||
| } | ||
| } | ||
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| bool AIEUnallocatedSuperRegRewriter::runOnMachineFunction(MachineFunction &MF) { | ||
| LLVM_DEBUG(llvm::dbgs() << "*** Splitting unallocated super-registers: " | ||
| << MF.getName() << " ***\n"); | ||
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| MachineRegisterInfo &MRI = MF.getRegInfo(); | ||
| VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM(); | ||
| LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM(); | ||
| LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); | ||
| SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI(); | ||
| LiveDebugVariables &DebugVars = | ||
| getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV(); | ||
| auto &TRI = | ||
| *static_cast<const AIEBaseRegisterInfo *>(MRI.getTargetRegisterInfo()); | ||
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| LLVM_DEBUG(dbgs() << "Identifying rewrite candidates...\n"); | ||
| RegRewriteInfo RegistersToRewrite = getRewriteCandidates(MRI, TRI, VRM); | ||
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| if (RegistersToRewrite.empty()) { | ||
| LLVM_DEBUG(dbgs() << "No candidates found, skipping rewrite\n"); | ||
| return false; | ||
| } | ||
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| LLVM_DEBUG(dbgs() << "Performing register rewrites...\n"); | ||
| rewriteCandidates(RegistersToRewrite, MRI, TRI, VRM, LRM, LIS, Indexes, | ||
| DebugVars); | ||
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| LLVM_DEBUG(dbgs() << "Successfully rewrote " << RegistersToRewrite.size() | ||
| << " register(s)\n"); | ||
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| return !RegistersToRewrite.empty(); | ||
| } | ||
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| } // end anonymous namespace | ||
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| char AIEUnallocatedSuperRegRewriter::ID = 0; | ||
| char &llvm::AIEUnallocatedSuperRegRewriterID = | ||
| AIEUnallocatedSuperRegRewriter::ID; | ||
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| INITIALIZE_PASS(AIEUnallocatedSuperRegRewriter, | ||
| "aie-unallocated-superreg-rewrite", | ||
| "AIE unallocated super-reg rewrite", false, false) | ||
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| llvm::FunctionPass *llvm::createAIEUnallocatedSuperRegRewriter() { | ||
| return new AIEUnallocatedSuperRegRewriter(); | ||
| } | ||
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nit: const