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Description
If there are 2 modules with identical functionality, but different port names, match section doesn't link them.
module mod (
input clk,
input a,
output reg b
);
always @(posedge clk) b <= a;
endmodulemodule mod (
input clk,
input a,
output reg c
);
always @(posedge clk) c <= a;
endmodule[match *]
gate-match c b
ERROR: No matching port in gate module was found for \b!
As I can tell while running with --debug, combine.ys script is executed before matching and errors out on ports.
Sometimes during refactoring port names are changed too, so it would be convenient if old and new names could be matched as all other nets.
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