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unable to prove that yosys synthesis worked on gcd

Status: Open.

#88 In YosysHQ/eqy;

· oharboe opened on Dec 14, 2025

false positive(?) on floorplan .v file from OpenROAD

Status: Open.

#87 In YosysHQ/eqy;

· oharboe opened on Dec 14, 2025

False positive on pin swap

Status: Open.

#86 In YosysHQ/eqy;

· maliberty opened on Nov 26, 2025

False PASS in simple SAT example

Status: Open.

#83 In YosysHQ/eqy;

· stevehoover opened on Sep 6, 2025

Unable to prove that original gcd design and synthesized gcd design are logicaly equivalent

Status: Open.

#82 In YosysHQ/eqy;

· leeway64 opened on Aug 19, 2025

Eqy to check two files with different input names but same structures

Status: Open.

#80 In YosysHQ/eqy;

· meeeeeeeng opened on Jun 10, 2025

eqy fails in partitioning design

Status: Open.

#79 In YosysHQ/eqy;

· Manchdog opened on Jun 6, 2025

Matching fails, if comparing "register value is assigned to a wire" and "output is a register that is assigned"

Status: Open.

#78 In YosysHQ/eqy;

· georg-imms opened on Jun 4, 2025

Match doesn't work on module ports.

Status: Open.

#77 In YosysHQ/eqy;

· max-kudinov opened on Apr 15, 2025

Unexpected gate in partition that causes FAIL checking result

Status: Open.

#76 In YosysHQ/eqy;

· Manchdog opened on Jan 15, 2025

Comparing vhdl to verilog fails

Status: Open.

#75 In YosysHQ/eqy;

· Topi-ab opened on Jan 11, 2025

partition: ERROR: Found 2 problems in 'check -assert'.

Status: Open.

#73 In YosysHQ/eqy;

· cassiersg opened on Nov 13, 2024