Eqy to check two files with different input names but same structures

[meeeeeeeng]

I'm trying to check the equivalence of The EPFL Combinational Benchmark Suite, but when I was checking voter.v and voter.blif, I found the input ports name are different,for example the one in verilog are A[0] A[1] A[2] A[3] A[4]....while in gate are pi0000 pi0001 pi0002 pi0003...

They have same number of inputs and outputs. How can I check the equivalence of these two files?

i've tried to use match but it doesn't work

Here's the eqy file without using match.

[gold]
read_verilog voter.v
prep -top top

[gate]
read_blif voter_depth_2024.blif
rename /home/ei/workspace/wanghexi/result-2/tmp/1337_11_voter top
prep -top top
cd top

[partition *]
amend *

[match top]
gold-nomatch n*
gate-nomatch n*

[strategy simple]
use sat
depth 5