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widlarizerwidlarizer
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Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
write_rtlil: don't sort
2 parents b9dc578 + 0d8c211 commit a78eb9e

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19 files changed

+247
-109
lines changed

19 files changed

+247
-109
lines changed

‎Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -890,6 +890,7 @@ MK_TEST_DIRS += tests/sim
890890
MK_TEST_DIRS += tests/svtypes
891891
MK_TEST_DIRS += tests/techmap
892892
MK_TEST_DIRS += tests/various
893+
MK_TEST_DIRS += tests/rtlil
893894
ifeq ($(ENABLE_VERIFIC),1)
894895
ifneq ($(YOSYS_NOVERIFIC),1)
895896
MK_TEST_DIRS += tests/verific

‎backends/rtlil/rtlil_backend.cc‎

Lines changed: 74 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -24,12 +24,23 @@
2424

2525
#include "rtlil_backend.h"
2626
#include "kernel/yosys.h"
27+
#include "kernel/utils.h"
2728
#include <errno.h>
29+
#include <iterator>
2830

2931
USING_YOSYS_NAMESPACE
3032
using namespace RTLIL_BACKEND;
3133
YOSYS_NAMESPACE_BEGIN
3234

35+
void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj)
36+
{
37+
for (const auto& [name, value] : reversed(obj->attributes)) {
38+
f << stringf("%s" "attribute %s ", indent, name);
39+
dump_const(f, value);
40+
f << stringf("\n");
41+
}
42+
}
43+
3344
void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
3445
{
3546
if (width < 0)
@@ -110,8 +121,8 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
110121
dump_sigchunk(f, sig.as_chunk(), autoint);
111122
} else {
112123
f << stringf("{ ");
113-
for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
114-
dump_sigchunk(f, *it, false);
124+
for (const auto& chunk : reversed(sig.chunks())) {
125+
dump_sigchunk(f, chunk, false);
115126
f << stringf(" ");
116127
}
117128
f << stringf("}");
@@ -120,14 +131,10 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
120131

121132
void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
122133
{
123-
for (auto &it : wire->attributes) {
124-
f << stringf("%s" "attribute %s ", indent, it.first);
125-
dump_const(f, it.second);
126-
f << stringf("\n");
127-
}
134+
dump_attributes(f, indent, wire);
128135
if (wire->driverCell_) {
129136
f << stringf("%s" "# driver %s %s\n", indent,
130-
wire->driverCell()->name.c_str(), wire->driverPort().c_str());
137+
wire->driverCell()->name, wire->driverPort());
131138
}
132139
f << stringf("%s" "wire ", indent);
133140
if (wire->width != 1)
@@ -149,11 +156,7 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
149156

150157
void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory)
151158
{
152-
for (auto &it : memory->attributes) {
153-
f << stringf("%s" "attribute %s ", indent, it.first);
154-
dump_const(f, it.second);
155-
f << stringf("\n");
156-
}
159+
dump_attributes(f, indent, memory);
157160
f << stringf("%s" "memory ", indent);
158161
if (memory->width != 1)
159162
f << stringf("width %d ", memory->width);
@@ -166,71 +169,58 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL
166169

167170
void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
168171
{
169-
for (auto &it : cell->attributes) {
170-
f << stringf("%s" "attribute %s ", indent, it.first);
171-
dump_const(f, it.second);
172-
f << stringf("\n");
173-
}
172+
dump_attributes(f, indent, cell);
174173
f << stringf("%s" "cell %s %s\n", indent, cell->type, cell->name);
175-
for (auto &it : cell->parameters) {
174+
for (const auto& [name, param] : reversed(cell->parameters)) {
176175
f << stringf("%s parameter%s%s %s ", indent,
177-
(it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
178-
(it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",
179-
it.first.c_str());
180-
dump_const(f, it.second);
176+
(param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
177+
(param.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",
178+
name);
179+
dump_const(f, param);
181180
f << stringf("\n");
182181
}
183-
for (auto &it : cell->connections()) {
184-
f << stringf("%s connect %s ", indent, it.first);
185-
dump_sigspec(f, it.second);
182+
for (const auto& [port, sig] : reversed(cell->connections_)) {
183+
f << stringf("%s connect %s ", indent, port);
184+
dump_sigspec(f, sig);
186185
f << stringf("\n");
187186
}
188187
f << stringf("%s" "end\n", indent);
189188
}
190189

191190
void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
192191
{
193-
for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
194-
{
192+
for (const auto& [lhs, rhs] : cs->actions) {
195193
f << stringf("%s" "assign ", indent);
196-
dump_sigspec(f, it->first);
194+
dump_sigspec(f, lhs);
197195
f << stringf(" ");
198-
dump_sigspec(f, it->second);
196+
dump_sigspec(f, rhs);
199197
f << stringf("\n");
200198
}
201199

202-
for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
203-
dump_proc_switch(f, indent, *it);
200+
for (const auto& sw : cs->switches)
201+
dump_proc_switch(f, indent, sw);
204202
}
205203

206204
void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw)
207205
{
208-
for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) {
209-
f << stringf("%s" "attribute %s ", indent, it->first);
210-
dump_const(f, it->second);
211-
f << stringf("\n");
212-
}
206+
dump_attributes(f, indent, sw);
213207

214208
f << stringf("%s" "switch ", indent);
215209
dump_sigspec(f, sw->signal);
216210
f << stringf("\n");
217211

218-
for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
212+
for (const auto case_ : sw->cases)
219213
{
220-
for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
221-
f << stringf("%s attribute %s ", indent, ait->first);
222-
dump_const(f, ait->second);
223-
f << stringf("\n");
224-
}
214+
dump_attributes(f, indent, case_);
225215
f << stringf("%s case ", indent);
226-
for (size_t i = 0; i < (*it)->compare.size(); i++) {
216+
for (size_t i = 0; i < case_->compare.size(); i++) {
227217
if (i > 0)
228218
f << stringf(" , ");
229-
dump_sigspec(f, (*it)->compare[i]);
219+
dump_sigspec(f, case_->compare[i]);
230220
}
231221
f << stringf("\n");
232222

233-
dump_proc_case_body(f, indent + " ", *it);
223+
dump_proc_case_body(f, indent + " ", case_);
234224
}
235225

236226
f << stringf("%s" "end\n", indent);
@@ -253,20 +243,16 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
253243
case RTLIL::STi: f << stringf("init\n"); break;
254244
}
255245

256-
for (auto &it: sy->actions) {
246+
for (const auto& [lhs, rhs] : sy->actions) {
257247
f << stringf("%s update ", indent);
258-
dump_sigspec(f, it.first);
248+
dump_sigspec(f, lhs);
259249
f << stringf(" ");
260-
dump_sigspec(f, it.second);
250+
dump_sigspec(f, rhs);
261251
f << stringf("\n");
262252
}
263253

264254
for (auto &it: sy->mem_write_actions) {
265-
for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) {
266-
f << stringf("%s attribute %s ", indent, it2->first);
267-
dump_const(f, it2->second);
268-
f << stringf("\n");
269-
}
255+
dump_attributes(f, indent, &it);
270256
f << stringf("%s memwr %s ", indent, it.memid);
271257
dump_sigspec(f, it.address);
272258
f << stringf(" ");
@@ -281,15 +267,11 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
281267

282268
void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc)
283269
{
284-
for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) {
285-
f << stringf("%s" "attribute %s ", indent, it->first);
286-
dump_const(f, it->second);
287-
f << stringf("\n");
288-
}
270+
dump_attributes(f, indent, proc);
289271
f << stringf("%s" "process %s\n", indent, proc->name);
290272
dump_proc_case_body(f, indent + " ", &proc->root_case);
291-
for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
292-
dump_proc_sync(f, indent + " ", *it);
273+
for (auto* sync : proc->syncs)
274+
dump_proc_sync(f, indent + " ", sync);
293275
f << stringf("%s" "end\n", indent);
294276
}
295277

@@ -309,11 +291,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
309291

310292
if (print_header)
311293
{
312-
for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) {
313-
f << stringf("%s" "attribute %s ", indent, it->first);
314-
dump_const(f, it->second);
315-
f << stringf("\n");
316-
}
294+
dump_attributes(f, indent, module);
317295

318296
f << stringf("%s" "module %s\n", indent, module->name);
319297

@@ -335,40 +313,40 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
335313

336314
if (print_body)
337315
{
338-
for (auto it : module->wires())
339-
if (!only_selected || design->selected(module, it)) {
316+
for (const auto& [_, wire] : reversed(module->wires_))
317+
if (!only_selected || design->selected(module, wire)) {
340318
if (only_selected)
341319
f << stringf("\n");
342-
dump_wire(f, indent + " ", it);
320+
dump_wire(f, indent + " ", wire);
343321
}
344322

345-
for (auto it : module->memories)
346-
if (!only_selected || design->selected(module, it.second)) {
323+
for (const auto& [_, mem] : reversed(module->memories))
324+
if (!only_selected || design->selected(module, mem)) {
347325
if (only_selected)
348326
f << stringf("\n");
349-
dump_memory(f, indent + " ", it.second);
327+
dump_memory(f, indent + " ", mem);
350328
}
351329

352-
for (auto it : module->cells())
353-
if (!only_selected || design->selected(module, it)) {
330+
for (const auto& [_, cell] : reversed(module->cells_))
331+
if (!only_selected || design->selected(module, cell)) {
354332
if (only_selected)
355333
f << stringf("\n");
356-
dump_cell(f, indent + " ", it);
334+
dump_cell(f, indent + " ", cell);
357335
}
358336

359-
for (auto it : module->processes)
360-
if (!only_selected || design->selected(module, it.second)) {
337+
for (const auto& [_, process] : reversed(module->processes))
338+
if (!only_selected || design->selected(module, process)) {
361339
if (only_selected)
362340
f << stringf("\n");
363-
dump_proc(f, indent + " ", it.second);
341+
dump_proc(f, indent + " ", process);
364342
}
365343

366344
bool first_conn_line = true;
367-
for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
345+
for (const auto& [lhs, rhs] : module->connections()) {
368346
bool show_conn = !only_selected || design->selected_whole_module(module->name);
369347
if (!show_conn) {
370-
RTLIL::SigSpec sigs = it->first;
371-
sigs.append(it->second);
348+
RTLIL::SigSpec sigs = lhs;
349+
sigs.append(rhs);
372350
for (auto &c : sigs.chunks()) {
373351
if (c.wire == NULL || !design->selected(module, c.wire))
374352
continue;
@@ -378,7 +356,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
378356
if (show_conn) {
379357
if (only_selected && first_conn_line)
380358
f << stringf("\n");
381-
dump_conn(f, indent + " ", it->first, it->second);
359+
dump_conn(f, indent + " ", lhs, rhs);
382360
first_conn_line = false;
383361
}
384362
}
@@ -394,7 +372,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
394372

395373
if (!flag_m) {
396374
int count_selected_mods = 0;
397-
for (auto module : design->modules()) {
375+
for (auto* module : design->modules()) {
398376
if (design->selected_whole_module(module->name))
399377
flag_m = true;
400378
if (design->selected(module))
@@ -410,7 +388,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
410388
f << stringf("autoidx %d\n", autoidx);
411389
}
412390

413-
for (auto module : design->modules()) {
391+
for (const auto& [_, module] : reversed(design->modules_)) {
414392
if (!only_selected || design->selected(module)) {
415393
if (only_selected)
416394
f << stringf("\n");
@@ -438,10 +416,14 @@ struct RTLILBackend : public Backend {
438416
log(" -selected\n");
439417
log(" only write selected parts of the design.\n");
440418
log("\n");
419+
log(" -sort\n");
420+
log(" sort design in-place (used to be default).\n");
421+
log("\n");
441422
}
442423
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
443424
{
444425
bool selected = false;
426+
bool do_sort = false;
445427

446428
log_header(design, "Executing RTLIL backend.\n");
447429

@@ -452,14 +434,19 @@ struct RTLILBackend : public Backend {
452434
selected = true;
453435
continue;
454436
}
437+
if (arg == "-sort") {
438+
do_sort = true;
439+
continue;
440+
}
455441
break;
456442
}
457443
extra_args(f, filename, args, argidx);
458444

459-
design->sort();
460-
461445
log("Output filename: %s\n", filename);
462446

447+
if (do_sort)
448+
design->sort();
449+
463450
*f << stringf("# Generated by %s\n", yosys_maybe_version());
464451
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
465452
}
@@ -528,7 +515,7 @@ struct DumpPass : public Pass {
528515
if (!empty) {
529516
rewrite_filename(filename);
530517
std::ofstream *ff = new std::ofstream;
531-
ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
518+
ff->open(filename, append ? std::ofstream::app : std::ofstream::trunc);
532519
if (ff->fail()) {
533520
delete ff;
534521
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));

‎backends/rtlil/rtlil_backend.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
YOSYS_NAMESPACE_BEGIN
3232

3333
namespace RTLIL_BACKEND {
34+
void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj);
3435
void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true);
3536
void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true);
3637
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true);

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