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Add Optimization Barriers #4763

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1f3328a
kernel: define $barrier cell
georgerennie Nov 20, 2024
c0576de
opt_merge: don't merge $barrier cells
georgerennie Nov 20, 2024
ff848ba
write_aiger2: support $barrier
georgerennie Nov 20, 2024
fc35002
write_btor: support $barrier, $buf and $_BUF_
georgerennie Nov 20, 2024
0c488dc
write_firrtl: support $buf and $barrier
georgerennie Nov 20, 2024
b1ff31c
write_smt2: support $buf and $barrier
georgerennie Nov 20, 2024
7813f53
write_verilog: support $barrier
georgerennie Nov 20, 2024
6be0d85
flatten: add -barriers flag
georgerennie Nov 20, 2024
268394b
optbarriers: add command to add/remove optimization barriers
georgerennie Nov 20, 2024
2663d31
prep: add -barriers flag
georgerennie Nov 20, 2024
6de8141
optbarriers: add -noconns option
georgerennie Dec 2, 2024
d191c41
optbarriers: preserve SCCs in processes
georgerennie Dec 2, 2024
5f26e66
optbarriers: comment typo
georgerennie Dec 2, 2024
d1eeae5
write_smt2: only take sign of cell if fit has one
georgerennie Jul 15, 2025
5b06807
kernel: remove $barrier from cellaigs and satgen
georgerennie Jul 15, 2025
2b9926e
flatten: assert output isn't a constant when flattening with barriers
georgerennie Jul 15, 2025
24a9cbe
tests: add optbarriers tests
georgerennie Jul 15, 2025
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6 changes: 3 additions & 3 deletions backends/aiger2/aiger.cc
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Expand Up @@ -28,8 +28,8 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), \
ID($bwmux)
#define BITWISE_OPS ID($buf), ID($barrier), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), \
ID($fa), ID($bwmux)

#define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)

Expand Down Expand Up @@ -332,7 +332,7 @@ struct Index {
a = CFALSE;
}

if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) {
if (cell->type.in(ID($buf), ID($barrier), ID($pos), ID($_BUF_))) {
return a;
} else if (cell->type.in(ID($not), ID($_NOT_))) {
return NOT(a);
Expand Down
6 changes: 3 additions & 3 deletions backends/btor/btor.cc
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Expand Up @@ -509,7 +509,7 @@ struct BtorWorker
goto okay;
}

if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos)))
if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_), ID($barrier)))
{
string btor_op;
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
Expand All @@ -521,9 +521,9 @@ struct BtorWorker
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
SigSpec sig = sigmap(cell->getPort(ID::Y));

// the $pos cell just passes through, all other cells need an actual operation applied
// buffer cells just pass through, all other cells need an actual operation applied
int nid = nid_a;
if (cell->type != ID($pos))
if (!cell->type.in(ID($pos), ID($buf), ID($_BUF_), ID($barrier)))
{
log_assert(!btor_op.empty());
int sid = get_bv_sid(width);
Expand Down
2 changes: 1 addition & 1 deletion backends/firrtl/firrtl.cc
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Expand Up @@ -966,7 +966,7 @@ struct FirrtlWorker
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
if (cell->type == ID($pos)) {
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@povik povik Dec 16, 2024

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It's strange this interprets $pos without looking at the A_SIGNED parameter, but if there's a bug it's pre-existing

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@georgerennie georgerennie Jul 15, 2025

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Yeah I think its fine to leave as is for now

if (cell->type.in(ID($pos), ID($buf), ID($barrier))) {
// assign y = a;
// printCell(cell);
string a_expr = make_expr(cell->getPort(ID::A));
Expand Down
4 changes: 2 additions & 2 deletions backends/smt2/smt2.cc
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Expand Up @@ -460,7 +460,7 @@ struct Smt2Worker
{
RTLIL::SigSpec sig_a, sig_b;
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
bool is_signed = type == 'U' ? false : cell->getParam(ID::A_SIGNED).as_bool();
bool is_signed = type == 'U' ? false : cell->hasParam(ID::A_SIGNED) && cell->getParam(ID::A_SIGNED).as_bool();
int width = GetSize(sig_y);

if (type == 's' || type == 'S' || type == 'd' || type == 'b') {
Expand Down Expand Up @@ -678,7 +678,7 @@ struct Smt2Worker
if (cell->type == ID($eqx)) return export_bvop(cell, "(= A B)", 'b');

if (cell->type == ID($not)) return export_bvop(cell, "(bvnot A)");
if (cell->type == ID($pos)) return export_bvop(cell, "A");
if (cell->type.in(ID($pos), ID($buf), ID($barrier))) return export_bvop(cell, "A");
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@povik povik Dec 16, 2024

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I think this will crash when given a $buf or $barrier as those don't have A_SIGNED

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@georgerennie georgerennie Jul 15, 2025

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Agreed, have updated export_bvop to only check for A_SIGNED if it exists

if (cell->type == ID($neg)) return export_bvop(cell, "(bvneg A)");

if (cell->type == ID($add)) return export_bvop(cell, "(bvadd A B)");
Expand Down
2 changes: 1 addition & 1 deletion backends/verilog/verilog_backend.cc
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Expand Up @@ -1096,7 +1096,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}

if (cell->type.in(ID($_BUF_), ID($buf))) {
if (cell->type.in(ID($_BUF_), ID($buf), ID($barrier))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
Expand Down
4 changes: 2 additions & 2 deletions kernel/celledges.cc
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Expand Up @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN

void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
bool is_signed = !cell->type.in(ID($buf), ID($barrier)) && cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));

Expand Down Expand Up @@ -392,7 +392,7 @@ PRIVATE_NAMESPACE_END

bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
{
if (cell->type.in(ID($not), ID($pos), ID($buf))) {
if (cell->type.in(ID($not), ID($pos), ID($buf), ID($barrier))) {
bitwise_unary_op(this, cell);
return true;
}
Expand Down
2 changes: 2 additions & 0 deletions kernel/celltypes.h
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Expand Up @@ -87,6 +87,8 @@ struct CellTypes
{
setup_internals_eval();

setup_type(ID($barrier), {ID::A}, {ID::Y});

setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);

setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
Expand Down
2 changes: 1 addition & 1 deletion kernel/qcsat.cc
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Expand Up @@ -77,7 +77,7 @@ void QuickConeSat::prepare()

int QuickConeSat::cell_complexity(RTLIL::Cell *cell)
{
if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($buf), ID($_BUF_)))
if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($buf), ID($barrier), ID($_BUF_)))
return 0;
if (cell->type.in(ID($not), ID($and), ID($or), ID($xor), ID($xnor),
ID($reduce_and), ID($reduce_or), ID($reduce_xor),
Expand Down
9 changes: 5 additions & 4 deletions kernel/rtlil.cc
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Expand Up @@ -1466,7 +1466,7 @@ namespace {
cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
return;

if (cell->type == ID($buf)) {
if (cell->type.in(ID($buf), ID($barrier))) {
port(ID::A, param(ID::WIDTH));
port(ID::Y, param(ID::WIDTH));
check_expected();
Expand Down Expand Up @@ -2979,7 +2979,8 @@ DEF_METHOD(LogicNot, 1, ID($logic_not))
add ## _func(name, sig_a, sig_y, is_signed, src); \
return sig_y; \
}
DEF_METHOD(Buf, sig_a.size(), ID($buf))
DEF_METHOD(Buf, sig_a.size(), ID($buf))
DEF_METHOD(Barrier, sig_a.size(), ID($barrier))
#undef DEF_METHOD

#define DEF_METHOD(_func, _y_size, _type) \
Expand Down Expand Up @@ -4281,9 +4282,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
return;

if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux)) {
if (type.in(ID($buf), ID($barrier), ID($mux), ID($pmux), ID($bmux))) {
parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
if (type != ID($buf) && type != ID($mux))
if (!type.in(ID($buf), ID($barrier), ID($mux)))
parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
check();
return;
Expand Down
18 changes: 10 additions & 8 deletions kernel/rtlil.h
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Expand Up @@ -1613,10 +1613,11 @@ struct RTLIL::Module : public RTLIL::NamedObject

// The add* methods create a cell and return the created cell. All signals must exist in advance.

RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addBarrier (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");

RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
Expand Down Expand Up @@ -1748,10 +1749,11 @@ struct RTLIL::Module : public RTLIL::NamedObject

// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.

RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Barrier (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");

RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
Expand Down
1 change: 1 addition & 0 deletions passes/cmds/Makefile.inc
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Expand Up @@ -56,3 +56,4 @@ OBJS += passes/cmds/setenv.o
OBJS += passes/cmds/abstract.o
OBJS += passes/cmds/test_select.o
OBJS += passes/cmds/timeest.o
OBJS += passes/cmds/optbarriers.o
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