a4lg · a4lg · Feb 6, 2023 · Feb 5, 2023 · Aug 21, 2023
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
@@ -1184,10 +1184,12 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcb", "zca",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
+  {"smcsrind", "zicsr",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
+  {"sscsrind", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
   {"svadu", "zicsr",		check_implicit_always},
@@ -1331,10 +1333,12 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcntrpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smcsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sscsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svadu",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
@@ -74,14 +74,20 @@ enum riscv_csr_class
   CSR_CLASS_H_32,	/* hypervisor, rv32 only */
   CSR_CLASS_SMAIA,		/* Smaia */
   CSR_CLASS_SMAIA_32,		/* Smaia, rv32 only */
+  CSR_CLASS_SMAIA_OR_SMCSRIND,	/* Smaia or Smcsrind */
   CSR_CLASS_SMCNTRPMF,		/* Smcntrpmf */
   CSR_CLASS_SMCNTRPMF_32,	/* Smcntrpmf, rv32 only */
+  CSR_CLASS_SMCSRIND,		/* Smcsrind */
   CSR_CLASS_SMSTATEEN,		/* Smstateen only */
   CSR_CLASS_SMSTATEEN_32,	/* Smstateen RV32 only */
   CSR_CLASS_SSAIA,		/* Ssaia */
   CSR_CLASS_SSAIA_AND_H,	/* Ssaia with H */
   CSR_CLASS_SSAIA_32,		/* Ssaia, rv32 only */
   CSR_CLASS_SSAIA_AND_H_32,	/* Ssaia with H, rv32 only */
+  CSR_CLASS_SSAIA_OR_SSCSRIND,		/* Ssaia or Sscsrind */
+  CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H,	/* Ssaia or Sscsrind (with H) */
+  CSR_CLASS_SSCSRIND,		/* Sscsrind */
+  CSR_CLASS_SSCSRIND_AND_H,	/* Sscsrind (with H) */
   CSR_CLASS_SSSTATEEN,		/* S[ms]stateen only */
   CSR_CLASS_SSSTATEEN_AND_H,	/* S[ms]stateen only (with H) */
   CSR_CLASS_SSSTATEEN_AND_H_32,	/* S[ms]stateen RV32 only (with H) */
@@ -1022,6 +1028,8 @@ riscv_csr_address (const char *csr_name,
   bool need_check_version = false;
   bool is_rv32_only = false;
   bool is_h_required = false;
+  bool is_csr_req_complex = false;
+  bool csr_ok = false;
   const char* extension = NULL;
 
   switch (csr_class)
@@ -1054,13 +1062,22 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_SMAIA:
       extension = "smaia";
       break;
+    case CSR_CLASS_SMAIA_OR_SMCSRIND:
+      is_csr_req_complex = true;
+      extension = _ ("smaia' or `smcsrind");
+      csr_ok = (riscv_subset_supports (&riscv_rps_as, "smaia")
+		|| riscv_subset_supports (&riscv_rps_as, "smcsrind"));
+      break;
     case CSR_CLASS_SMCNTRPMF_32:
       is_rv32_only = true;
       /* Fall through.  */
     case CSR_CLASS_SMCNTRPMF:
       need_check_version = true;
       extension = "smcntrpmf";
       break;
+    case CSR_CLASS_SMCSRIND:
+      extension = "smcsrind";
+      break;
     case CSR_CLASS_SMSTATEEN_32:
       is_rv32_only = true;
       /* Fall through.  */
@@ -1092,6 +1109,21 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_SSCOFPMF:
       extension = "sscofpmf";
       break;
+    case CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H:
+      is_h_required = true;
+      /* Fall through.  */
+    case CSR_CLASS_SSAIA_OR_SSCSRIND:
+      is_csr_req_complex = true;
+      extension = _ ("ssaia' or `sscsrind");
+      csr_ok = (riscv_subset_supports (&riscv_rps_as, "ssaia")
+		|| riscv_subset_supports (&riscv_rps_as, "sscsrind"));
+      break;
+    case CSR_CLASS_SSCSRIND_AND_H:
+      is_h_required = true;
+      /* Fall through.  */
+    case CSR_CLASS_SSCSRIND:
+      extension = "sscsrind";
+      break;
     case CSR_CLASS_SSTC:
     case CSR_CLASS_SSTC_AND_H:
     case CSR_CLASS_SSTC_32:
@@ -1115,8 +1147,10 @@ riscv_csr_address (const char *csr_name,
       if (is_h_required && !riscv_subset_supports (&riscv_rps_as, "h"))
 	as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name);
 
-      if (extension != NULL
-	  && !riscv_subset_supports (&riscv_rps_as, extension))
+      if (is_csr_req_complex
+	      ? !csr_ok
+	      : (extension != NULL
+		 && !riscv_subset_supports (&riscv_rps_as, extension)))
 	as_warn (_("invalid CSR `%s', needs `%s' extension"),
 		 csr_name, extension);
     }

diff --git a/gas/testsuite/gas/riscv/csr-complex-1.d b/gas/testsuite/gas/riscv/csr-complex-1.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zicsr -mcsr-check
+#source: csr-complex.s
+#warning_output: csr-complex-1.l
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+35002573[ 	]+csrr[ 	]+a0,miselect
diff --git a/gas/testsuite/gas/riscv/csr-complex-1.l b/gas/testsuite/gas/riscv/csr-complex-1.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension
diff --git a/gas/testsuite/gas/riscv/csr-complex-2.d b/gas/testsuite/gas/riscv/csr-complex-2.d
@@ -0,0 +1,11 @@
+#as: -march=rv64i_zicsr_smaia -mcsr-check
+#source: csr-complex.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+35002573[ 	]+csrr[ 	]+a0,miselect
diff --git a/gas/testsuite/gas/riscv/csr-complex-3.d b/gas/testsuite/gas/riscv/csr-complex-3.d
@@ -0,0 +1,11 @@
+#as: -march=rv64i_zicsr_smcsrind -mcsr-check
+#source: csr-complex.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+35002573[ 	]+csrr[ 	]+a0,miselect
diff --git a/gas/testsuite/gas/riscv/csr-complex.s b/gas/testsuite/gas/riscv/csr-complex.s
@@ -0,0 +1,2 @@
+target:
+	csrr	a0, miselect
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -328,6 +328,11 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4898 \(minstretcfg\) at cfa\+3208
   DW_CFA_offset_extended_sf: r5921 \(mcyclecfgh\) at cfa\+7300
   DW_CFA_offset_extended_sf: r5922 \(minstretcfgh\) at cfa\+7304
+  DW_CFA_offset_extended_sf: r4946 \(mireg2\) at cfa\+3400
+  DW_CFA_offset_extended_sf: r4947 \(mireg3\) at cfa\+3404
+  DW_CFA_offset_extended_sf: r4949 \(mireg4\) at cfa\+3412
+  DW_CFA_offset_extended_sf: r4950 \(mireg5\) at cfa\+3416
+  DW_CFA_offset_extended_sf: r4951 \(mireg6\) at cfa\+3420
   DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
   DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
   DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
@@ -399,6 +404,16 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r5949 \(mhpmevent29h\) at cfa\+7412
   DW_CFA_offset_extended_sf: r5950 \(mhpmevent30h\) at cfa\+7416
   DW_CFA_offset_extended_sf: r5951 \(mhpmevent31h\) at cfa\+7420
+  DW_CFA_offset_extended_sf: r4434 \(sireg2\) at cfa\+1352
+  DW_CFA_offset_extended_sf: r4435 \(sireg3\) at cfa\+1356
+  DW_CFA_offset_extended_sf: r4437 \(sireg4\) at cfa\+1364
+  DW_CFA_offset_extended_sf: r4438 \(sireg5\) at cfa\+1368
+  DW_CFA_offset_extended_sf: r4439 \(sireg6\) at cfa\+1372
+  DW_CFA_offset_extended_sf: r4690 \(vsireg2\) at cfa\+2376
+  DW_CFA_offset_extended_sf: r4691 \(vsireg3\) at cfa\+2380
+  DW_CFA_offset_extended_sf: r4693 \(vsireg4\) at cfa\+2388
+  DW_CFA_offset_extended_sf: r4694 \(vsireg5\) at cfa\+2392
+  DW_CFA_offset_extended_sf: r4695 \(vsireg6\) at cfa\+2396
   DW_CFA_offset_extended_sf: r4429 \(stimecmp\) at cfa\+1332
   DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396
   DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356

diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -326,6 +326,12 @@ _start:
 	.cfi_offset minstretcfg, 3208
 	.cfi_offset mcyclecfgh, 7300
 	.cfi_offset minstretcfgh, 7304
+	# Smcsrind extension (except miselect/mireg in Smaia)
+	.cfi_offset mireg2, 3400
+	.cfi_offset mireg3, 3404
+	.cfi_offset mireg4, 3412
+	.cfi_offset mireg5, 3416
+	.cfi_offset mireg6, 3420
 	# Smstateen extension
 	.cfi_offset mstateen0, 3120
 	.cfi_offset mstateen1, 3124
@@ -400,6 +406,17 @@ _start:
 	.cfi_offset mhpmevent29h, 7412
 	.cfi_offset mhpmevent30h, 7416
 	.cfi_offset mhpmevent31h, 7420
+	# Sscsrind extension (except {v,}si{select,reg} in Ssaia)
+	.cfi_offset sireg2, 1352
+	.cfi_offset sireg3, 1356
+	.cfi_offset sireg4, 1364
+	.cfi_offset sireg5, 1368
+	.cfi_offset sireg6, 1372
+	.cfi_offset vsireg2, 2376
+	.cfi_offset vsireg3, 2380
+	.cfi_offset vsireg4, 2388
+	.cfi_offset vsireg5, 2392
+	.cfi_offset vsireg6, 2396
 	# Sstc extension
 	.cfi_offset stimecmp, 1332
 	.cfi_offset stimecmph, 1396

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -631,6 +631,16 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+35202573[ 	]+csrr[ 	]+a0,mireg2
+[ 	]+[0-9a-f]+:[ 	]+35259073[ 	]+csrw[ 	]+mireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+35302573[ 	]+csrr[ 	]+a0,mireg3
+[ 	]+[0-9a-f]+:[ 	]+35359073[ 	]+csrw[ 	]+mireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+35502573[ 	]+csrr[ 	]+a0,mireg4
+[ 	]+[0-9a-f]+:[ 	]+35559073[ 	]+csrw[ 	]+mireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+35602573[ 	]+csrr[ 	]+a0,mireg5
+[ 	]+[0-9a-f]+:[ 	]+35659073[ 	]+csrw[ 	]+mireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+35702573[ 	]+csrr[ 	]+a0,mireg6
+[ 	]+[0-9a-f]+:[ 	]+35759073[ 	]+csrw[ 	]+mireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
@@ -773,6 +783,26 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+73e59073[ 	]+csrw[ 	]+mhpmevent30h,a1
 [ 	]+[0-9a-f]+:[ 	]+73f02573[ 	]+csrr[ 	]+a0,mhpmevent31h
 [ 	]+[0-9a-f]+:[ 	]+73f59073[ 	]+csrw[ 	]+mhpmevent31h,a1
+[ 	]+[0-9a-f]+:[ 	]+15202573[ 	]+csrr[ 	]+a0,sireg2
+[ 	]+[0-9a-f]+:[ 	]+15259073[ 	]+csrw[ 	]+sireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+15302573[ 	]+csrr[ 	]+a0,sireg3
+[ 	]+[0-9a-f]+:[ 	]+15359073[ 	]+csrw[ 	]+sireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+15502573[ 	]+csrr[ 	]+a0,sireg4
+[ 	]+[0-9a-f]+:[ 	]+15559073[ 	]+csrw[ 	]+sireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+15602573[ 	]+csrr[ 	]+a0,sireg5
+[ 	]+[0-9a-f]+:[ 	]+15659073[ 	]+csrw[ 	]+sireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+15702573[ 	]+csrr[ 	]+a0,sireg6
+[ 	]+[0-9a-f]+:[ 	]+15759073[ 	]+csrw[ 	]+sireg6,a1
+[ 	]+[0-9a-f]+:[ 	]+25202573[ 	]+csrr[ 	]+a0,vsireg2
+[ 	]+[0-9a-f]+:[ 	]+25259073[ 	]+csrw[ 	]+vsireg2,a1
+[ 	]+[0-9a-f]+:[ 	]+25302573[ 	]+csrr[ 	]+a0,vsireg3
+[ 	]+[0-9a-f]+:[ 	]+25359073[ 	]+csrw[ 	]+vsireg3,a1
+[ 	]+[0-9a-f]+:[ 	]+25502573[ 	]+csrr[ 	]+a0,vsireg4
+[ 	]+[0-9a-f]+:[ 	]+25559073[ 	]+csrw[ 	]+vsireg4,a1
+[ 	]+[0-9a-f]+:[ 	]+25602573[ 	]+csrr[ 	]+a0,vsireg5
+[ 	]+[0-9a-f]+:[ 	]+25659073[ 	]+csrw[ 	]+vsireg5,a1
+[ 	]+[0-9a-f]+:[ 	]+25702573[ 	]+csrr[ 	]+a0,vsireg6
+[ 	]+[0-9a-f]+:[ 	]+25759073[ 	]+csrw[ 	]+vsireg6,a1
 [ 	]+[0-9a-f]+:[ 	]+14d02573[ 	]+csrr[ 	]+a0,stimecmp
 [ 	]+[0-9a-f]+:[ 	]+14d59073[ 	]+csrw[ 	]+stimecmp,a1
 [ 	]+[0-9a-f]+:[ 	]+15d02573[ 	]+csrr[ 	]+a0,stimecmph
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		.*Assembler messages:
		.*Warning: invalid CSR `miselect', needs `smaia' or `smcsrind' extension