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Draft Extension: Smcdeleg and Ssccfg #126

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@a4lg a4lg commented Aug 8, 2023

@a4lg a4lg added the enhancement New feature or request label Aug 8, 2023
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch from 21c3bc4 to 8a7b085 Compare August 11, 2023 01:54
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from 49246e0 to cc271b4 Compare August 11, 2023 03:56
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch 2 times, most recently from 3f850c8 to 1d9d8c3 Compare August 15, 2023 06:37
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from 11d9ed4 to 94c835e Compare August 15, 2023 07:27
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch from 1d9d8c3 to 70eb2da Compare August 15, 2023 07:27
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch from 70eb2da to 6b0a0f9 Compare September 3, 2023 02:26
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from 14d0f6b to eab6063 Compare September 3, 2023 02:41
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch 3 times, most recently from 68f6465 to 816fc17 Compare September 5, 2023 04:57
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from eab6063 to 75c034c Compare September 5, 2023 07:58
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch 2 times, most recently from 219136e to c949835 Compare September 7, 2023 09:35
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from ae50984 to a1c1b5b Compare October 16, 2023 09:05
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch from c949835 to 8bd1e8b Compare October 16, 2023 09:05
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from a1c1b5b to 2fbc260 Compare October 19, 2023 01:17
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch from 8bd1e8b to c0ab4e4 Compare October 19, 2023 03:17
a4lg added 5 commits October 19, 2023 06:58
@a4lg
RISC-V: Base for complex extension implications
e4d4e27 
Thanks to the commit 48558a5 ("RISC-V: Allow nested implications for
extensions"), we can write complex extension implications in theory.
However, to actually do that, we need to pass more information to
check_func.

For example, we want to imply 'Zcf' from 'F' if and only if the 'Zce'
extension is also enabled and XLEN is 32.  Passing rps is a way to
enable this.

This commit prepares for such complex extension implications.

bfd/ChangeLog:

	* elfxx-riscv.c (struct riscv_implicit_subset): Move around and
	change check_func function prototype.
	(check_implicit_always): New arguments.
	(check_implicit_for_i): Likewise.
	(riscv_implicit_subsets): Add comment for this variable.
	(riscv_parse_add_implicit_subsets): Call check_func with
	new arguments.
@a4lg
RISC-V: Add 'Zicntr' and 'Zihpm' support with compatibility measures
f3c2a5c 
This commit adds support for 'Zicntr' and 'Zihpm' extensions (version 2.0).

However, because GNU Binutils handled those as a part of 'I' and there was
a time when a ratified specification did split counters from the 'I'
extension without separate extension names.

To preserve maximum compatibility, this commit implements as follows:

*   For RISC-V ISA version 20191213 or less (all current non-draft ones),
    imply counter extensions from 'I' and DO NOT imply the 'Zicsr' extension
    from counter extensions.  We also suppress outputting the existence of
    counter extensions unless the version number is explicitly specified.
*   For future ratified ISAs, leave two options (each require minor edits):
    *   Continue previous behaviors or
    *   DO NOT imply counter extensions from 'I'.  DO imply the 'Zicsr'
        extension from counter extensions.  DO NOT suppress outputting the
        existence of such counter extensions by having a known
        version number (version 2.0 or [though unlikely] later).
        Make small changes to the disassembler to keep compatibility when
        disassembling old files.

bfd/ChangeLog:

	* elfxx-riscv.c (check_implicit_compat_counter_from_i): New function
	for counter compatibility from 'I' to counter extensions.
	(check_implicit_compat_counter_to_zicsr): New function for counter
	compatibility from counter extensions to the 'Zicsr' extension.
	(riscv_implicit_subsets): Add implications related to counter
	extensions with compatibility measures.
	(riscv_supported_std_z_ext): Add 'Zicntr' and 'Zihpm' extensions.
	But make version "unknown" to suppress outputting implicit
	dependencies on older ISAs.
	(riscv_parse_add_subset): Add "zicntr" and "zihpm" to exceptions
	to recognize on older ISAs if there's no version number.
	(riscv_multi_subset_supports): Add support for 'Zicntr'.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	'Zicntr' and 'Zihpm' extensions.
	(riscv_csr_address): Add handling for new CSR classes.
	* testsuite/gas/riscv/march-imply-i.s: Add 'Zicntr' instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Change CSR classes for counter CSRs.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICNTR
	for 'Zicntr' pseudoinstructions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Recategorize counter
	pseudoinstructions to the 'Zicntr' extension.
@a4lg
RISC-V: Add complex CSR error handling
62bf546 
This commit adds template for complex CSR error handling (such like
multiple extensions involved).

gas/ChangeLog:

	* config/tc-riscv.c (riscv_csr_address): Add complex CSR error
	handling.
@a4lg
UNRATIFIED RISC-V: Add indirect CSR Access Extensions and its CSRs
f91776e 
[DO NOT MERGE]
Until the Indirect CSR Access Architecture Extension is frozen/ratified and
final version number is determined, this patch should not be merged
upstream.  This commit uses placeholder version 0.1 because there's no
version number in the current documentation.

This commit adds indirect CSR access extensions (Smcsrind / Sscsrind) and
their CSRs based on the latest documentation (as of 2023-08-07):
<https://docs.google.com/document/d/1ZxTSUWX_9_VafWeA0l1ci9RFjmivLuZn-US9IbFOEWY>

Because six CSRs are duplicates of 'Smaia' / 'Ssaia' extensions, it adds
complex CSR handling for those.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implications
	'Smcsrind' / 'Sscsrind' -> 'Zicsr'.
	(riscv_supported_std_s_ext): Add 'Smcsrind' and 'Sscsrind'
	extensions to the valid 'S' extension list.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	the 'S[ms]csrind' extensions. (riscv_csr_address): Add handling for
	new CSR classes.
	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr.s: Add new CSRs.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h: Recategory miselect, mireg, siselect, sireg,
	vsiselect and vsireg CSRs. (CSR_MIREG2, CSR_MIREG3, CSR_MIREG4,
	CSR_MIREG5, CSR_MIREG6, CSR_SIREG2, CSR_SIREG3, CSR_SIREG4,
	CSR_SIREG5, CSR_SIREG6, CSR_VSIREG2, CSR_VSIREG3, CSR_VSIREG3,
	CSR_VSIREG5, CSR_VSIREG6): Add new.
@a4lg
UNRATIFIED RISC-V: Add supervisor counter delegation extensions
e7d54eb 
[DO NOT MERGE]
Until the Supervisor Counter Delegation Architecture Extension is frozen /
ratified and final version number is determined, this patch should not be
merged upstream. This commit uses version 0.1 as a placeholder because
there's no version number in the current documentation.

This commit adds support for two extensions from the Supervisor Counter
Delegation Architecture Extension specification ('Smcdeleg' and 'Ssccfg')
based on the latest documentation (as of 2023-08-07):
<https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add related implications
	including the ones to 'Zicsr' for compatibility and excluding
	the ones to counter extensions that require *either* 'Zicntr' or
	'Zihpm'.
	(riscv_supported_std_s_ext): Add 'Smcdeleg' and 'Ssccfg' extensions
	to the supported 'S' extension list.
	(riscv_parse_check_conflicts): Check existence of either 'Zicntr' or
	'Zihpm' if either 'Smcdeleg' or 'Ssccfg' is enabled.
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch from 1ae2bb7 to f3c2a5c Compare October 19, 2023 07:01
@a4lg a4lg force-pushed the riscv-smcdeleg-ssccfg branch from c0ab4e4 to e7d54eb Compare October 19, 2023 07:01
@a4lg a4lg force-pushed the riscv-zicntr-zihpm branch 3 times, most recently from 872554c to a155952 Compare October 21, 2023 03:44
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