Patches Withdrawn

2023

• Draft Extension: Ssecorrupt (RAS Exceptions and Interrupts) (as the extension is dropped)
• Draft Extension: ZiCond (Conditional Operations)
  (Philipp Tomsich upstreamed the support)
• Draft Extension: Zfa (Misc. Basic scalar FP)
  (Christoph Müllner et al. upstreamed the support; my work is partially used)
• Draft Extension: Zisslpcfi (CFI: Shadow Stacks and Landing Pads)
  (due to intensive specification changes and new extension names, new implementation will get a new branch)

2022

• Disassembler: Fix zip / unzip on disassembler
  (superseded by Disassembler: Make some instruction non-aliases)
• Disassembler: Rounding mode on widening instructions
  (superseded by Disassembler: Support special (non-standard) encodings)
• Disassembler: Use xlen on ADDIW address sequence
  (superseded by Disassembler: Core improvements and optimizations (batch 1))
• Disassembler: Use faster hash table
  (superseded by Disassembler: Core improvements and optimizations (batch 1))
• Disassembler: Minor optimizations (batch 1)
  (superseded by Disassembler: Core improvements and optimizations (batch 1))
• Disassembler: Cache instruction class support
  (superseded by Disassembler: Core improvements and optimizations (batch 1))
• Disassembler: Add arch disassembler option
  (superseded by Disassembler: Add overridable priv-spec and arch options)
• Disassembler: Make ELF priv-spec overridable
  (superseded by Disassembler: Add overridable priv-spec and arch options)
• Disassembler: Check shift amount against XLEN (Idea 1)
  (withdrawn and superseded by Disassembler: Check shift amount against XLEN (Idea 2))
• Disassembler: Fix printf types on riscv-dis.c
  (superseded by Disassembler: Fix types and styles)
• Disassembler: Core improvements and optimizations (batch 1)
  (superseded by Disassembler: Core Optimization 1-1 (Hash table and Caching))
• Disassembler: Core improvements and optimizations (batch 2)
  (superseded by Disassembler: Core Optimization 1-2 (Mapping symbols))
• RISC-V: Fix CSR accessibility and implications
  (as it contains multiple discussions, we must split it)
• Combined floating point enhancements
  (superseded by RISC-V: Zfinx-related fixes (1) and ongoing changes)
• Disassembler: Make some instruction non-aliases
  (Jan upstreamed roughly equivalent patch)
• sim/testsuite: Trim extra path from arch
  (Mike Frysinger fixed the bug with different approach)
• RISC-V: Support mapping symbols with ISA string
  (implemented by Nelson)
• GAS: Mapping symbol with ISA string whenever non-default architecture is used
  (Some clarification is required and Nelson will fix at least the assembler side)
• Disassembler: Support special (non-standard) encodings
  (will be superseded by multiple patchsets)
• GAS Testsuite: Use real extension names (B / K)
  (will be superseded by another testing patchset)
• Draft Extension: Zfb
  (withdrawn because of additional instructions and rename from Zfb to Zfa but kept for educational purposes)
• Draft Extension: ZiCondOps (Conditional Operations)
  (superseded by Draft Extension: ZiCond)