riscv_zvef_allow_zfinx

Extension: Zve32f, Zve64f and Zve64d with Zfinx-based configuration

• Status: WITHDRAWN
  (I referred the "V" spec "1.0" but that's public review version and not ratified one)
• Branch: riscv-zvef-allow-zfinx
• Tracking PR: #117 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2023-08-03)
  • PATCH v2 (2023-08-03)

Feature Description

In the RISC-V "V" Vector Extension specification, it states that Zve*f require either F or Zfinx and Zve64d requires either D or Zdinx.

Current Binutils lacks support for following configurations:

• Zve32f and Zfinx
• Zve64f and Zfinx
• Zve64d and Zdinx

The reason behind it is probably because Zfinx and Zdinx are not ratified at the time when the V support is added.

Since all V, Zfinx and Zdinx are ratified, it's time to implement vector configurations for embedded systems as this commit does.

This commit doesn't normally affect the programs that use the V extension since it does not allow Zfinx-based configuration. However, if the program is compiled with Zve*[fd] extensions, it might need additional F or Zfinx extension to the "-march" option.

Note that all F registers are replaced to even-numbered X registers (GPRs) in the new instruction test.