riscv_dis_opts_cache_support

Disassembler: Cache instruction class support

• Status: Waiting for a prerequisite to be Merged
• Branch: riscv-dis-opts-cache-support
• Tracking PR: #22 (view Pull Request and Diff)
• Mailing List:
  • Not yet

Requires

• Disassembler: Minor optimizations (batch 1)
  • Requires: Disassembler: Use faster hash table

Project: Disassembler Performance Improvements

1. Disassembler: Use faster hash table
2. Disassembler: Minor optimizations (batch 1)
3. (You are here) Disassembler: Cache instruction class support

Feature Description

As I mentioned in the previous patchset, calling riscv_subset_supports repeatedly harms the performance in a measurable way (about 3-13% in total).

As a simple solution, this patch now caches instruction class support as a signed char array.

Performance Improvements

On disassembling linked RISC-V ELF files using objdump, performance improvements achieved by this patchset is about 6-8%. Not bad for a simple change.

This is relative to the previous optimization.

TODO: PATCH 1/7 of riscv-dis-opts-minor-1 is slightly changed since the last benchmark. Although the performance impact of this modification is marginal (almost zero), rerun the benchmark before submission.

objdump (near regular cases)

Program	Improvements
Busybox 1.35.1 (RV64GC)	6.3-6.9%
OpenSBI 1.1 (generic fw_*.elf)	5.8-7.4%
Linux kernel 5.18 (vmlinux)	6.0-7.5%
Linux kernel 5.18 (vmlinux.o)	(-1.5)-2.4%
glibc (libc.so.6)	6.3-6.9%
glibc (libc.a)	(-0.8)-(-0.4)%
newlib (libc.a)	(-0.6)-1.2%

objdump (special cases)

Program	Improvements
Random files (/dev/urandom)	7.4-7.9%
1M (1048576) CSR instructions	34.8%

gdb: disas of near all code region

Program	Improvements
Linux kernel 5.18 (vmlinux) with debug info	0.8%
Linux kernel 5.18 (vmlinux) without debug info	1.3%
OpenSBI 1.1 (generic fw_*.elf)	0.4-5.8%