riscv_dis_support_special_encodings_1

Disassembler: Support special (non-standard) encodings (widening FP ops)

• Branch: riscv-dis-support-special-encodings-1
• Tracking PR: #96 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-11-28)

Based On

• Disassembler: Support special (non-standard) encodings
  (this patchset was a part of it)

Issue Solved

Some of the floating point instructions does not depend on the rounding mode despite the existence of rm (rounding mode) field. Such examples are widening conversion instructions.

Quoting "11.2 Floating-Point Control and Status Register" from the RISC-V ISA Manual (version 20191213):

Some instructions, including widening conversions, have the rm field but are nevertheless unaffected by the rounding mode; software should set their rm field to RNE (000).

The latest draft of the ISA Manual is clarified further:

Quoting "13.2 Floating-Point Control and Status Register" from the RISC-V ISA Manual (version draft-20221119-5234c63):

Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to RNE (000) but implementations must treat the rm field as usual (in particular, with regard to decoding legal vs. reserved encodings).

For instance, to encode a FCVT.D.S instruction, we should set its rm field to RNE (0b000). However, FCVT.D.S instruction with non-RNE rm field is still a valid instruction (despite that GAS does not allow specifying any rounding modes on FCVT.D.S) and must handle as a valid instruction when disassembled unless an invalid rounding mode is specified.

However, current GNU Binutils only supports disassembling widening conversion instructions with rm field of RNE (0b000) except FCVT.Q.L and FCVT.Q.LU instructions (two instructions supported specifying rounding modes for historical reasons).

This patchset (in specific, the commit "RISC-V: Rounding mode on widening instructions") enables special handling of such instructions by adding two new operand types:

1. "WfM":
   Optional rounding mode where specifying rounding mode is not supported in the past.
2. "Wfm":
   Optional rounding mode where specifying rounding mode is supported in the past (used in FCVT.Q.L and FCVT.Q.LU).

I designed this patchset to be configurable (allow implementing S Pawan Kumar's proposal if needed) but the behavior in this patchset is as follows:

On the disassembler, optional (non-RNE [≠ 0b000]) rounding mode is printed only if:

1. "no-aliases" disassembler option is specified, or
2. the rounding mode is invalid (0b101 / 0b110).

I think removing condition (1) might be an option. Because, despite that we can now see the actual rounding mode with condition (1), it's not valid as an assembler mnemonic.

Condition (2) is an intentional choice to detect invalid encodings. Still, it could be removed, too (I don't recommend though).

On the assembler, specifying optional rounding mode is prohibited (except FCVT.Q.L and FCVT.Q.LU) or accepted with a warning (FCVT.Q.L and FCVT.Q.LU).