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riscv_ext_rv32ef_fix
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riscv-ext-rv32ef-fix - Tracking PR: #50 (view Pull Request and Diff)
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RV32EF combination is no longer prohibited by the ISA Manual.
This restriction is introduced in binutils' RV32E support commit 7f99954970001cfc1b155d877ac2966d77e2c647. At that time, the latest ratified version of the RISC-V ISA Manual (version 2.2) stated that F extension requires I base.
However, the next ratified version of the RISC-V ISA Manual (20190608-Base-Ratified) removed such limitation.
Although this combination is not prohibited, because RV32E is only used with a soft-float calling convention, there's no official ABIs that fully support RV32EF.
It means, even if we can assemble a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept in an unmanaged state (outside ABI management).
The purpose of this commit is to suppress unnecessary errors while parsing an ISA string and/or disassembling, not to allow hard-float with RVE.