FPGA-Based Acceleration of Active Learning for Image Classification

This repository provides the hardware and software implementations used for accelerating an active learning query strategy applied to image classification tasks.

Hardware Implementation

The hardware design files are located in: hw_design/MarginSampling512_4608/

• Verilog source files:
  hw_design/MarginSampling512_4608/src/

• Deployment notebook:
  hw_design/MarginSampling512_4608/MarginSampling512_4608.ipynb

Software Implementations

Due to size limitations, the Google Colab notebooks for the software experiments are provided via external links:

Model	Dataset	Notebook Link
MobileNetV1	Fashion-MNIST
MobileNetV1	CIFAR-10
EfficientNetB0	Fashion-MNIST
EfficientNetB0	CIFAR-10
ResNet50	Fashion-MNIST
ResNet50	CIFAR-10