The caching invalidation guidelines from the AMD-Vi...
High severity
Unreviewed
Published
Jan 5, 2024
to the GitHub Advisory Database
•
Updated Jun 18, 2025
Description
Published by the National Vulnerability Database
Jan 5, 2024
Published to the GitHub Advisory Database
Jan 5, 2024
Last updated
Jun 18, 2025
The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.
References