[sw-sysemu]: Changes to run sysemu within cosim context #58
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A few notes:
Please clean it up, and I would personally prefer a separate emu.mk for erbium. or comment that this is for erbium. |
cosim doesn't SP PLIC to exist (wasn't present in bemu). When it was added to sysemu, SYS_EMU guard was inconsistent: it disabled headers, but not the sp_plic region, thus failing to compile. This change disables SP PLIC as it always was in cosim context.
When compiling in cosim context, different logger version is substituted that has no buffer dump functionality.
When sysemu is used in cosim context, it is compiled using c++11 standard. Modern amenities must go.
Each version (emu-et.mk and emu-er.mk) will be used to build different breeds of cosim. Cosim will handle emu_x.mk selection itself.
Omission appeared after compiling without SYS_EMU defined.
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@glguida
The SP PLIC was never available in bemu, and while cosim may potentially live with it added, I decided not to risk introducing changes at this moment. Also, apparently it didn't even compile in non-SYS_EMU mode before.
It was indeed for ET-SoC-1 build of cosim so we could verify integration with known passing tests. Now that it's done, I've added another commit that "splits" |
| /* sram */ 0x000200E000ull, | ||
| /* dram */ 0x0040000000ull, /* Actually MRAM */ | ||
| /* sysreg */ 0x0080000000ull, | ||
| /* plic */ 0x00C0000000ull, |
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The grouping separators are useful for readability. Why are you removing them?
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@tahoma
In cosim context sysemu source is compiled as part of DV/cosim source tree, where several things are set to build with c++11 standard. Modifying the DV infrastructure to work with c++17 headers isn't easily achievable.
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Ah, okay. That's unfortunate. Thank you for the explanation.
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| #endif // EMU_HAS_SVCPROC | ||
| #endif // EMU_HAS_SVCPROC && SYS_EMU |
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#endif // EMU_HAS_SVCPROC && defined(SYS_EMU)
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Lol, I was really distracted when I saw this. Nope, this is fine. Merging. |
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Sysemu among other things is designed to take a role of co-simulator in DV checking of the chips it emulates.
Changes here fix what has diverged from the last time it was used in cosim context.
This PR only supports running ET-SoC-1 cosim. Erbium related changes to follow.