Skip to content

Fixed some parameter and ref placement#4

Open
SZBihan wants to merge 1 commit intoalexforencich:masterfrom
SZBihan:master
Open

Fixed some parameter and ref placement#4
SZBihan wants to merge 1 commit intoalexforencich:masterfrom
SZBihan:master

Conversation

@SZBihan
Copy link

@SZBihan SZBihan commented Aug 13, 2025

Changed some parameter and reg placements to comply with modern Verilog standards. Tested to work with iverilog v13 (was failing before)

…og standards. Tested to work with iverilog v13 (was failing before)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant