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alexforencichalexforencich
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Add UPDATE_TID parameter to set MSBs of tid based on source port
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12 files changed

+246
-61
lines changed

12 files changed

+246
-61
lines changed

‎rtl/axis_arb_mux.v‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ module axis_arb_mux #
5757
parameter USER_WIDTH = 1,
5858
// Propagate tlast signal
5959
parameter LAST_ENABLE = 1,
60+
// Update tid with routing information
61+
parameter UPDATE_TID = 0,
6062
// select round robin arbitration
6163
parameter ARB_TYPE_ROUND_ROBIN = 0,
6264
// LSB priority selection
@@ -93,6 +95,21 @@ module axis_arb_mux #
9395

9496
parameter CL_S_COUNT = $clog2(S_COUNT);
9597

98+
// check configuration
99+
initial begin
100+
if (UPDATE_TID) begin
101+
if (!ID_ENABLE) begin
102+
$error("Error: UPDATE_TID set requires ID_ENABLE set (instance %m)");
103+
$finish;
104+
end
105+
106+
if (M_ID_WIDTH < CL_S_COUNT) begin
107+
$error("Error: M_ID_WIDTH too small for port count (instance %m)");
108+
$finish;
109+
end
110+
end
111+
end
112+
96113
wire [S_COUNT-1:0] request;
97114
wire [S_COUNT-1:0] acknowledge;
98115
wire [S_COUNT-1:0] grant;
@@ -150,6 +167,9 @@ always @* begin
150167
m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid;
151168
m_axis_tlast_int = current_s_tlast;
152169
m_axis_tid_int = current_s_tid;
170+
if (UPDATE_TID && S_COUNT > 1) begin
171+
m_axis_tid_int[M_ID_WIDTH-1:M_ID_WIDTH-CL_S_COUNT] = grant_encoded;
172+
end
153173
m_axis_tdest_int = current_s_tdest;
154174
m_axis_tuser_int = current_s_tuser;
155175
end

‎rtl/axis_arb_mux_wrap.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,8 @@ def generate(ports=4, name=None, output=None):
9292
parameter USER_WIDTH = 1,
9393
// Propagate tlast signal
9494
parameter LAST_ENABLE = 1,
95+
// Update tid with routing information
96+
parameter UPDATE_TID = 0,
9597
// select round robin arbitration
9698
parameter ARB_TYPE_ROUND_ROBIN = 0,
9799
// LSB priority selection
@@ -140,6 +142,7 @@ def generate(ports=4, name=None, output=None):
140142
.USER_ENABLE(USER_ENABLE),
141143
.USER_WIDTH(USER_WIDTH),
142144
.LAST_ENABLE(LAST_ENABLE),
145+
.UPDATE_TID(UPDATE_TID),
143146
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
144147
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
145148
)

‎rtl/axis_ram_switch.v‎

Lines changed: 36 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,8 @@ module axis_ram_switch #
9696
// Interface connection control
9797
// M_COUNT concatenated fields of S_COUNT bits
9898
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
99+
// Update tid with routing information
100+
parameter UPDATE_TID = 0,
99101
// select round robin arbitration
100102
parameter ARB_TYPE_ROUND_ROBIN = 1,
101103
// LSB priority selection
@@ -188,6 +190,18 @@ initial begin
188190
$finish;
189191
end
190192

193+
if (UPDATE_TID) begin
194+
if (!ID_ENABLE) begin
195+
$error("Error: UPDATE_TID set requires ID_ENABLE set (instance %m)");
196+
$finish;
197+
end
198+
199+
if (M_ID_WIDTH < CL_S_COUNT) begin
200+
$error("Error: M_ID_WIDTH too small for port count (instance %m)");
201+
$finish;
202+
end
203+
end
204+
191205
if (M_BASE == 0) begin
192206
// M_BASE is zero, route with tdest as port index
193207
$display("Addressing configuration for axis_switch instance %m");
@@ -825,16 +839,30 @@ generate
825839
);
826840

827841
// mux
828-
wire [RAM_ADDR_WIDTH-1:0] cmd_addr_mux = int_cmd_addr[grant_encoded*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH];
829-
wire [ADDR_WIDTH-1:0] cmd_len_mux = int_cmd_len[grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
830-
wire [CMD_ADDR_WIDTH-1:0] cmd_id_mux = int_cmd_id[grant_encoded*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH];
831-
wire [KEEP_WIDTH-1:0] cmd_tkeep_mux = int_cmd_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
832-
wire [M_ID_WIDTH-1:0] cmd_tid_mux = int_cmd_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
833-
wire [M_DEST_WIDTH-1:0] cmd_tdest_mux = int_cmd_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH];
834-
wire [USER_WIDTH-1:0] cmd_tuser_mux = int_cmd_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
835-
wire cmd_valid_mux = int_cmd_valid[grant_encoded*M_COUNT+n] && grant_valid;
842+
reg [RAM_ADDR_WIDTH-1:0] cmd_addr_mux;
843+
reg [ADDR_WIDTH-1:0] cmd_len_mux;
844+
reg [CMD_ADDR_WIDTH-1:0] cmd_id_mux;
845+
reg [KEEP_WIDTH-1:0] cmd_tkeep_mux;
846+
reg [M_ID_WIDTH-1:0] cmd_tid_mux;
847+
reg [M_DEST_WIDTH-1:0] cmd_tdest_mux;
848+
reg [USER_WIDTH-1:0] cmd_tuser_mux;
849+
reg cmd_valid_mux;
836850
wire cmd_ready_mux;
837851

852+
always @* begin
853+
cmd_addr_mux = int_cmd_addr[grant_encoded*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH];
854+
cmd_len_mux = int_cmd_len[grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
855+
cmd_id_mux = int_cmd_id[grant_encoded*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH];
856+
cmd_tkeep_mux = int_cmd_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
857+
cmd_tid_mux = int_cmd_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
858+
if (UPDATE_TID && S_COUNT > 1) begin
859+
cmd_tid_mux[M_ID_WIDTH-1:M_ID_WIDTH-CL_S_COUNT] = grant_encoded;
860+
end
861+
cmd_tdest_mux = int_cmd_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH];
862+
cmd_tuser_mux = int_cmd_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
863+
cmd_valid_mux = int_cmd_valid[grant_encoded*M_COUNT+n] && grant_valid;
864+
end
865+
838866
assign int_cmd_ready[n*S_COUNT +: S_COUNT] = (grant_valid && cmd_ready_mux) << grant_encoded;
839867

840868
for (m = 0; m < S_COUNT; m = m + 1) begin

‎rtl/axis_ram_switch_wrap.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,8 @@ def generate(ports=4, name=None, output=None):
132132
// Interface connection control
133133
parameter M{{'%02d'%p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
134134
{%- endfor %}
135+
// Update tid with routing information
136+
parameter UPDATE_TID = 0,
135137
// select round robin arbitration
136138
parameter ARB_TYPE_ROUND_ROBIN = 1,
137139
// LSB priority selection
@@ -212,6 +214,7 @@ def generate(ports=4, name=None, output=None):
212214
.M_BASE({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_BASE){% if not loop.last %}, {% endif %}{% endfor %} }),
213215
.M_TOP({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_TOP){% if not loop.last %}, {% endif %}{% endfor %} }),
214216
.M_CONNECT({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT){% if not loop.last %}, {% endif %}{% endfor %} }),
217+
.UPDATE_TID(UPDATE_TID),
215218
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
216219
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
217220
.RAM_PIPELINE(RAM_PIPELINE)

‎rtl/axis_switch.v‎

Lines changed: 34 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,8 @@ module axis_switch #
7171
// Interface connection control
7272
// M_COUNT concatenated fields of S_COUNT bits
7373
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
74+
// Update tid with routing information
75+
parameter UPDATE_TID = 0,
7476
// Input interface register type
7577
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
7678
parameter S_REG_TYPE = 0,
@@ -123,6 +125,18 @@ initial begin
123125
$finish;
124126
end
125127

128+
if (UPDATE_TID) begin
129+
if (!ID_ENABLE) begin
130+
$error("Error: UPDATE_TID set requires ID_ENABLE set (instance %m)");
131+
$finish;
132+
end
133+
134+
if (M_ID_WIDTH < CL_S_COUNT) begin
135+
$error("Error: M_ID_WIDTH too small for port count (instance %m)");
136+
$finish;
137+
end
138+
end
139+
126140
if (M_BASE == 0) begin
127141
// M_BASE is zero, route with tdest as port index
128142
$display("Addressing configuration for axis_switch instance %m");
@@ -320,14 +334,27 @@ generate
320334
);
321335

322336
// mux
323-
wire [DATA_WIDTH-1:0] m_axis_tdata_mux = int_s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
324-
wire [KEEP_WIDTH-1:0] m_axis_tkeep_mux = int_s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
325-
wire m_axis_tvalid_mux = int_axis_tvalid[grant_encoded*M_COUNT+n] && grant_valid;
337+
reg [DATA_WIDTH-1:0] m_axis_tdata_mux;
338+
reg [KEEP_WIDTH-1:0] m_axis_tkeep_mux;
339+
reg m_axis_tvalid_mux;
326340
wire m_axis_tready_mux;
327-
wire m_axis_tlast_mux = int_s_axis_tlast[grant_encoded];
328-
wire [M_ID_WIDTH-1:0] m_axis_tid_mux = int_s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
329-
wire [M_DEST_WIDTH-1:0] m_axis_tdest_mux = int_s_axis_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH];
330-
wire [USER_WIDTH-1:0] m_axis_tuser_mux = int_s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
341+
reg m_axis_tlast_mux;
342+
reg [M_ID_WIDTH-1:0] m_axis_tid_mux;
343+
reg [M_DEST_WIDTH-1:0] m_axis_tdest_mux;
344+
reg [USER_WIDTH-1:0] m_axis_tuser_mux;
345+
346+
always @* begin
347+
m_axis_tdata_mux = int_s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
348+
m_axis_tkeep_mux = int_s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
349+
m_axis_tvalid_mux = int_axis_tvalid[grant_encoded*M_COUNT+n] && grant_valid;
350+
m_axis_tlast_mux = int_s_axis_tlast[grant_encoded];
351+
m_axis_tid_mux = int_s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
352+
if (UPDATE_TID && S_COUNT > 1) begin
353+
m_axis_tid_mux[M_ID_WIDTH-1:M_ID_WIDTH-CL_S_COUNT] = grant_encoded;
354+
end
355+
m_axis_tdest_mux = int_s_axis_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH];
356+
m_axis_tuser_mux = int_s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
357+
end
331358

332359
assign int_axis_tready[n*S_COUNT +: S_COUNT] = (grant_valid && m_axis_tready_mux) << grant_encoded;
333360

‎rtl/axis_switch_wrap.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,8 @@ def generate(ports=4, name=None, output=None):
107107
// Interface connection control
108108
parameter M{{'%02d'%p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
109109
{%- endfor %}
110+
// Update tid with routing information
111+
parameter UPDATE_TID = 0,
110112
// Input interface register type
111113
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
112114
parameter S_REG_TYPE = 0,
@@ -175,6 +177,7 @@ def generate(ports=4, name=None, output=None):
175177
.M_BASE({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_BASE){% if not loop.last %}, {% endif %}{% endfor %} }),
176178
.M_TOP({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_TOP){% if not loop.last %}, {% endif %}{% endfor %} }),
177179
.M_CONNECT({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT){% if not loop.last %}, {% endif %}{% endfor %} }),
180+
.UPDATE_TID(UPDATE_TID),
178181
.S_REG_TYPE(S_REG_TYPE),
179182
.M_REG_TYPE(M_REG_TYPE),
180183
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),

‎tb/axis_arb_mux/Makefile‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ export PARAM_DEST_WIDTH ?= 8
4949
export PARAM_USER_ENABLE ?= 1
5050
export PARAM_USER_WIDTH ?= 1
5151
export PARAM_LAST_ENABLE ?= 1
52+
export PARAM_UPDATE_TID ?= 1
5253
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
5354
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
5455

@@ -66,6 +67,7 @@ ifeq ($(SIM), icarus)
6667
COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE)
6768
COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
6869
COMPILE_ARGS += -P $(TOPLEVEL).LAST_ENABLE=$(PARAM_LAST_ENABLE)
70+
COMPILE_ARGS += -P $(TOPLEVEL).UPDATE_TID=$(PARAM_UPDATE_TID)
6971
COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
7072
COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
7173

@@ -87,6 +89,7 @@ else ifeq ($(SIM), verilator)
8789
COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE)
8890
COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
8991
COMPILE_ARGS += -GLAST_ENABLE=$(PARAM_LAST_ENABLE)
92+
COMPILE_ARGS += -GUPDATE_TID=$(PARAM_UPDATE_TID)
9093
COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
9194
COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
9295

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