FPGAlize 👋

FPGAlize is a self-hosted web platform that provides an interactive and visual environment for exploring FPGA signal behavior. 🖥️⚡ It allows users to observe, analyze, and manipulate signals in real time, making FPGA development more accessible for learners, researchers, and engineers.

🔑 Key Features

• 🎨 2D Visualization of BELs and signal routing
• ⚡ Real-time simulation with adjustable speed controls
• 📜 Preloaded Verilog Applications for educational use
• 👨‍🏫 Teacher Dashboard to upload Verilog files and testbenches

🚀 Installation

Tip

We recommend that you use our public demo by following this link.

Prerequisites 🛠️

Ensure you have the following installed:

• Node.js v23.7.0 or higher
• NPM v11.1.0 or higher

Install from GitHub 🏗️

1. Clone the repository:

   git clone https://github.com/algosup/2024-2025-project-4-web-fpga-team-7.git
   cd 2024-2025-project-4-web-fpga-team-7

2. Install dependencies and start the post-build server:

   cd Code/Frontend
   npm install
   npm run build
   npm run preview

3. Access the application at http://localhost:4173.

Note

You can start the server in Development Mode by running npm run dev and access the application at http://localhost:5173.

Caution

The dev branch contains the latest unstable features. Use at your own risk.

Alternative Installation via Scripts ⚙️

Windows (PowerShell):

cd Scripts
./win-setup.ps1

Linux/macOS:

cd Scripts
./unix-setup.sh

🐳 Quick Start with Docker

1. Pull and run the container (no need to build manually):

   docker pull ghcr.io/techxplorerfr/fpgalize:latest
   docker run -p 4173:4173 ghcr.io/techxplorerfr/fpgalize:latest

2. Access FPGAlize at http://localhost:4173.

🛠️ How to Add Custom Examples

Note

To add your own example to the application, you need to have access to your post-synthesis files, composed of a Standard Delay Format File (.sdf) and Verilog File (.v). We highly recommend you using AMD Vivado Design Suite to obtain those files.

To add your custom examples to FPGAlize:

1. Open the left drawer and click Import.
2. Drop your files in the corresponding field of the modal which appeared, and then click Create Example.

Your example is created and opened as the active tab.

📚 Documentation

• Functional Specifications
• Technical Specifications
• Project Charter
• Test Plan
• Test Cases
• User Manual

📜 License

This project is licensed under the MIT License.

💬 Support

We welcome your questions and suggestions. Feel free to open an issue in the Issue Section.

👥 Contributing

See the Contributing Guidelines for details on how to contribute.

✍️ Authors & Acknowledgments

Our Team 🚀

Name	Role	Links
Pierre GORIN	Project Manager	LinkedIn GitHub
Aurélien FERNANDEZ	Program Manager	LinkedIn GitHub
Abderrazaq MAKRAN	Technical Lead	LinkedIn GitHub
Guillaume DERAMCHI	Quality Assurance	LinkedIn GitHub
Enzo GUILLOUCHE	Software Engineer 1	LinkedIn GitHub
Antoine PREVOST	Software Engineer 2	LinkedIn GitHub
Max BERNARD	Technical Writer	LinkedIn GitHub

Happy coding with FPGAlize! 🎉