soc: alif: add HE_DMA_SEL LPSPI mux config to soc_init#453
soc: alif: add HE_DMA_SEL LPSPI mux config to soc_init#453sudhir-alifsemi wants to merge 1 commit intoalifsemi:mainfrom
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Configure the HE_DMA_SEL register for LPSPI during SoC initialization for both ensemble and balletto families. The DMA controller selection is derived at build time from the DTS dmas property of the LP-SPI node. E1C and B1 always use DMA2, with the register value determined by the DMA group. E3/E5/E7/E4/E6/E8 support both DMA2 and DMA0, detected via the event router phandle in the dmas specifier. Signed-off-by: Sudhir Sreedharan <sudhir@alifsemi.com>
sudhir-alifsemi
requested review from
RupeshKumar-AlifSemi,
Tanay-AlifSemi and
silesh-alifsemi
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Pull request overview
Configure the HE DMA controller selection (HE_DMA_SEL) for LP-SPI during SoC init by deriving the correct mux value from the devicetree dmas specifier for Ensemble and Balletto families.
Changes:
- Add HE_DMA_SEL LPSPI bitfield definitions to SoC common headers.
- Add devicetree-driven HE_DMA_SEL programming for LPSPI during
soc_init()on Ensemble (E1C + E-series) and Balletto (B1). - Detect DMA0 vs DMA2 on supported Ensemble E-series parts via the event-router phandle in
dmas.
Reviewed changes
Copilot reviewed 4 out of 4 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
| soc/alif/ensemble/common/soc_common.h | Adds HE_DMA_SEL LPSPI bit position/mask definitions. |
| soc/alif/ensemble/common/soc_common.c | Adds devicetree-driven HE_DMA_SEL configuration during SoC init for Ensemble variants. |
| soc/alif/balletto/common/soc_common.h | Adds HE_DMA_SEL LPSPI bit position/mask definitions. |
| soc/alif/balletto/common/soc_common.c | Adds devicetree-driven HE_DMA_SEL configuration during SoC init for Balletto B1. |
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| /* Configure HE_DMA_SEL mux for LP-SPI */ | ||
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi0), okay) && DT_NODE_HAS_PROP(DT_NODELABEL(lpspi0), dmas) | ||
| soc_configure_he_dma_sel_lpspi(); | ||
| #endif |
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Unlike the Ensemble implementation, the Balletto call path is not guarded by CONFIG_RTSS_HE, yet it writes M55HE_CFG_HE_DMA_SEL (an HE register). If RTSS_HE is disabled in a build, this can still compile and attempt to touch HE config registers during soc_init(). Wrap both the helper definition and the call site with the same IS_ENABLED(CONFIG_RTSS_HE) guard (or an equivalent existing SoC/RTSS guard used elsewhere in this file) so the HE register access cannot occur when HE/RTSS is not present/enabled.
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For Balletto we have only RTSS_HE which is implicit.
| #if DT_SAME_NODE(DT_PHANDLE_BY_IDX(DT_NODELABEL(spi4), dmas, 0), DT_NODELABEL(evtrtr2)) | ||
| sel_val = 0x0U; /* DMA2 selected */ | ||
| #else | ||
| /* DMA0 selected — determine group */ | ||
| uint32_t dma_group = ALIF_DMA_DECODE_GROUP( | ||
| DT_PHA_BY_IDX(DT_NODELABEL(spi4), dmas, 0, channel)); |
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This hard-codes DT_NODELABEL(evtrtr2). If a board/SoC DTS variant enables spi4 with dmas, but uses a different event-router node label (or lacks evtrtr2), referencing DT_NODELABEL(evtrtr2) can cause a devicetree compile failure. Prefer guarding the comparison with DT_NODE_EXISTS(DT_NODELABEL(evtrtr2)) (e.g., combine it into the #if), or avoid the fixed label by detecting DMA2 vs DMA0 purely from the dmas controller node in a way that doesn’t require a specific node label.
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Since the EVTRTR2 node is always present in RTSS_HE (enabled or otherwise), no compilation errors will occur
Configure the HE_DMA_SEL register for LPSPI during SoC initialization for both ensemble and balletto families. The DMA controller selection is derived at build time from the DTS dmas property of the LP-SPI node.
E1C and B1 always use DMA2, with the register value determined by the DMA group. E3/E5/E7/E4/E6/E8 support both DMA2 and DMA0, detected via the event router phandle in the dmas specifier.