Updating readme files

Author: paddy3696

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md

@@ -26,7 +26,7 @@
 ## Documentation
 
 - **Title**: Design Document
-- **URL**:https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
+**URL**:https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
 
 ## Build and Run Flow
 

niosv_g/niosv_g_webserver_ping/sources/README.md

@@ -31,7 +31,8 @@ Observe the Ping Request and Response prints on the terminal.
 
 ## Documentation
 
-- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/niosv_g_webserver_ping/docs/NiosV_g_Processor_ping_on_Agilex_5_FPGA.md
+- **Title**: Design Document 
+**URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/niosv_g_webserver_ping/docs/NiosV_g_Processor_ping_on_Agilex_5_FPGA.md
 
 
 # Getting Started

niosv_g/tinyml_liteRT/sources/README.md

@@ -10,22 +10,22 @@ This design demonstrates the TinyML application using LiteRT for microcontroller
 
 ## Project Details
 
-* **Title**: Agilex 5 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor
-* **Source**: Github
-* **Design Support**: CTH
-* **Family**: Agilex 5
-* **Quartus Version**: 25.3.0
-* **Development Kit**: Agilex 5 FPGA E*Series 065B Premium Development Kit DK*A5E065BB32AES1
-* **Device Part**: A5ED065BB32AE6SR0
-* **Design Package**: agilex5_niosv_g_tinyml_liteRT.zip
-* **Category**: Machine Learning
-* **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_g/tinyml_liteRT
-* **downloadURL**:https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3.0-v1.0/agilex5_niosv_g_tinyml_liteRT.zip
+- **Title**: Agilex 5 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor
+- **Source**: Github
+- **Design Support**: CTH
+- **Family**: Agilex 5
+- **Quartus Version**: 25.3.0
+- **Development Kit**: Agilex 5 FPGA E*Series 065B Premium Development Kit DK*A5E065BB32AES1
+- **Device Part**: A5ED065BB32AE6SR0
+- **Design Package**: agilex5_niosv_g_tinyml_liteRT.zip
+- **Category**: Machine Learning
+- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_g/tinyml_liteRT
+- **downloadURL**:https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3.0-v1.0/agilex5_niosv_g_tinyml_liteRT.zip
 
 ## Documentation
 
-* **Title**: Design Document 
-* **URL**:   https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/tinyml_liteRT/img/block_diagram.png
+- **Title**: Design Document 
+**URL**:   https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/tinyml_liteRT/img/block_diagram.png
 
 # Getting Started
 

niosv_m/niosv_m_full_feature_ghrd/sources/README.md

@@ -25,7 +25,7 @@ The objective of the design is to accomplish data transfer between the processor
 ## Documentation
 
 - **Title**: Design Document
-- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_m/niosv_m_full_feature_ghrd/docs/NiosV_m_Processor_full_feature_ghrd_on_Agilex_5_FPGA.md
+**URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_m/niosv_m_full_feature_ghrd/docs/NiosV_m_Processor_full_feature_ghrd_on_Agilex_5_FPGA.md
 
 # Getting Started