Design updates

Author: paddy3696

README.md

@@ -36,7 +36,7 @@ The following table contains the list of the designs on Agilex 5 FPGA E-Series 0
 
 | No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
 | - | --- | ------ | ----------- |
-| 1 | Nios V/m | Nios V/m Webserver Ping Design | This design demonstrates the transaction between the Nios® V processor with DMA and OCM core<br>[Design details](niosv_m/niosv_m_dma_ocm/docs/NiosV_m_Processor_DMA_OCM_Design_on_Agilex_5_FPGA.md) |
+| 1 | Nios V/g | Nios V/g Webserver Ping Design | This design demonstrates the Ping application using the Triple Speed Ethernet IP <br>[Design details](niosv_g/niosv_g_webserver_ping/docs/Nios_Vg_Processor_Webserver_Ping_Design_on_Agilex_5_FPGA.md) |
 | 2 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor<br>[Design details](niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_5_FPGA.md) |
 | 3 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md) |
-| 4 | Nios V/m | Nios V/m Full Feature Golden Hardware Reference Design (GHRD) | This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios V/m processor with basic bare minimum peripherals required for any application execution <br>[Design details](niosv_m/niosv_m_baseline_ghrd/docs/NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.md)|
+| 4 | Nios V/m | Nios V/m Full Feature Golden Hardware Reference Design (GHRD) | This design demonstrates the Full Feature Golden Hardware Reference Design (GHRD) that showcases the connectivity to multiple peripherals required for application execution <br>[Design details](niosv_m/niosv_m_full_feature_ghrd/docs/NiosV_m_Processor_full_feature_ghrd_on_Agilex_5_FPGA.md)|

niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md

@@ -13,14 +13,14 @@
 ### Release Contents  
 
 #### Binaries
- - Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
+ - Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
  - The sof and elf files required to run the design can be found in "ready_to_test" folder 
  - Program the sof and download the elf file on board
 
 ### Nios® V/c Helloworld OCM Memory test Design Architecture
  This example design includes a Nios® V/c processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
 
- ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
+ ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
 
 #### Nios® V/c Processor
 - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
@@ -79,10 +79,10 @@ Refer to [Agilex™ 5 FPGA Premium Development Kit User Guide](https://www.intel
 #### Tools Download and Installation
 1. Quartus Prime Pro
 
- - Download the Quartus® Prime Pro Edition software version 25.3 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
+ - Download the Quartus® Prime Pro Edition software version 25.3.0 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
  - Set up the Quartus tools in the PATH, so they are accessible without full path.
 ```console
-	export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.3/quartus/
+	export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.3.0/quartus/
 	export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH
 ```
 

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md

@@ -6,7 +6,7 @@
 
  Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
 
-![image](https://github.com/altera-fpga/niosv-ed/blob/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
+![image](https://github.com/altera-fpga/niosv-ed/blob/rel/25.3.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
 
 
 ## Project Details
@@ -20,13 +20,13 @@
 - **Device Part**: A5ED065BB32AE6SR0
 - **Design Package**: agilex5_niosv_c_helloworld_ocm_mem_test.zip
 - **Category**: Memory
-- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test
-- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1.1-v1.0/agilex5_niosv_c_helloworld_ocm_mem_test.zip
+- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_c/niosv_c_helloworld_ocm_mem_test
+- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3.0-v1.0/agilex5_niosv_c_helloworld_ocm_mem_test.zip
 
 ## Documentation
 
 - **Title**: Design Document
-- **URL**:https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
+- **URL**:https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
 
 ## Build and Run Flow