Merge pull request #7 from altera-fpga/bgadde/rel_25_1_1

Bgadde/rel 25 1 1

Author: ayerramr

README.md

@@ -1,9 +1,6 @@
 # Intel® Agilex™ 7 PCIe Root Port System Example Design
 
-This system example design demonstrates a PCIe root port running on the [Intel® Agilex™ 7 M-Series Development Kit](https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html) connected to a Non-Volatile Memory express (NVMe) endpoint. The PCIe root port is capable of Gen5x4 speeds. The design is intended to serve as a reference to customers on how to implement and run a performant root port system using the Intel® Agilex™ 7 SoC and relevant IP.
-
-For more information, refer to the [PCIe Root Port User Guide](https://altera-fpga.github.io/rel-24.3/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-agx7m-hbm2e/).
-
+This system example design demonstrates a PCIe root port.
 ## Description
 
 The PCIe root port example design is based on the Intel® Agilex™ 7 Golden System Reference Design (GSRD) with the following components added:
@@ -14,7 +11,7 @@ The PCIe root port example design is based on the Intel® Agilex™ 7 Golden Sys
 
 The system block diagram is shown below:
 
-![Intel® Agilex™ 7 M-Series Root Port block diagram](doc/R-Tile_RP.png)
+![Intel® Agilex™ 7 Root Port block diagram](doc/RP_Block_Diagram.png)
 
 - The HPS-to-FPGA (H2F) lightweight AXI-4 interface on the HPS is used for accessing the control and status (CSR) interface of various blocks on the design. It connects to the reconfiguration interface on the PCIe root port HIP as well as the Configuration Slave (CS) interface on the MCDMA bridge.
    - Configuration of the PCIe Endpoint (as part of Enumeration) is done via the CS interface. This interface supports only one outstanding config write/read transaction, as the number of PCIe tags allotted to this interface is only one (inside the MCDMA bridge).
@@ -31,19 +28,28 @@ Directory Structure used in this example design:
     |--- doc
     |--- src
     |   |--- hw
+	|   |  |--- ag7f014_devkit (Ptile-4x4)
+	|   |  |--- ag7i027_devkit (Ftile-2x4)
+	|   |  |--- ag7m039_devkit (Rtile-4x4)
+	
     |   |--- sw
+        |   |  |--- agilex7_dk_si_agf014eb-gsrd-build.sh   (Ptile-4x4)
+        |   |  |--- agilex7_dk_si_agi027fc-gsrd-build.sh   (Ftile-2x4)
+        |   |  |--- agilex7_dk_dev_agm039fes-rped-build.sh (Rtile-4x4)
  ```
 
 ## Project Details
 
 - **Family**: Intel® Agilex™ 7
-- **Quartus Version**: 24.3
-- **Development Kit**: [Intel® Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile)](https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html)
-- **Device Part**: AGMF039R47A1E2VR0
+- **Quartus Version**: 25.1.1
+
 
 ## Getting Started
 
 Follow the steps below to build the design:
 
-- [Building the hardware](src/hw/README.md)
-- [Building the software](src/sw/README.md)
+- [Building the P-Tile hardware](src/hw/ag7f014_devkit/README.md)
+- [Building the F-Tile hardware](src/hw/ag7i027_devkit/README.md)
+- [Building the R-Tile hardware](src/hw/ag7m039_devkit/README.md)
+
+- [Building the P-Tile F-Tile R-Tile software](src/sw/README.md)

doc/R-Tile_RP.png

@@ -0,0 +1,27 @@
+# Intel® Agilex™ 7 PCIe Root Port System Example Design Build Scripts
+
+This directory contains the Quartus Project for the Intel® Agilex™ 7 PCIe Root Port System Example Design.
+
+# Dependency
+
+- Intel® Quartus Prime (See Release Notes for the supported version)
+- Supported Board:
+  - (https://www.altera.com/products/devkit/a1jui0000061r0pmaq/agilex-7-fpga-f-series-transceiver-soc-development-kit-p-tile-and-e-tile)
+
+# Build Steps
+
+ 1. Compile design and generate configuration file:
+
+    ```
+    cd syn/
+	make all
+    ```
+
+# Programming Files Generation Steps
+
+ 1. Generate `top.{core,hps}.rbf` including U-Boot SPL:
+
+    ```
+    cd syn/
+    quartus_pfg -c -o hps=on -o hps_path=../../../sw/artifacts/ag7f014_devkit/u-boot-spl-dtb.hex output_files/top.sof output_files/top.rbf
+    ```