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preetam-narayanpreetam-narayan
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NET:ETH:ALTERA: checkpatch compliant for SDLE
Co-authored-by: Narayan, Preetam <[email protected]>
1 parent abe8b90 commit d8a0ed1

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48 files changed

+2819
-2817
lines changed

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_common_i2c.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
// SPDX-License-Identifier: GPL-2.0
22
/* Altera FPGA I2C client code
3-
* Copyright (C) 2023, 2025 Altera Corporation. All rights reserved
3+
* Copyright(C) 2023, 2025 Altera Corporation. All rights reserved
44
*
55
* Contributors:
66
*
77
*/
88

9-
#include "../intel_freq_control.h"
10-
#include "intel_freq_ctrl_common_i2c.h"
9+
#include "../intel_freq_control.h"
10+
#include "intel_freq_ctrl_common_i2c.h"
1111

1212
int determine_i2c_client(struct clock_cleaner *clockcleaner_info)
1313
{
@@ -18,10 +18,10 @@ int determine_i2c_client(struct clock_cleaner *clockcleaner_info)
1818
int ret = FREQ_CTRL_ERROR_FAIL;
1919
const char *type;
2020
struct i2c_client *i2c_cli;
21-
struct intel_freq_control_private *priv =
22-
container_of (clockcleaner_info,
23-
struct intel_freq_control_private,
24-
clockcleaner_info);
21+
struct intel_freq_control_private *priv =
22+
container_of(clockcleaner_info,
23+
struct intel_freq_control_private,
24+
clockcleaner_info);
2525

2626
i2c_cli = priv->fc_acc_type.i2c_cli;
2727

@@ -45,12 +45,12 @@ int determine_i2c_client(struct clock_cleaner *clockcleaner_info)
4545
ret = FREQ_CTRL_ERROR_FAIL;
4646
goto i2c_client_ret;
4747
}
48-
48+
4949
memset(&i2c_info, 0, sizeof(struct i2c_board_info));
5050
strscpy(i2c_info.type, type, I2C_NAME_SIZE);
5151
i2c_info.addr = addr;
5252
i2c_cli = i2c_new_client_device(i2c_adap, &i2c_info);
53-
53+
5454
if (IS_ERR(i2c_cli)) {
5555
pr_err("can't create i2c device %s\n", i2c_info.type);
5656
ret = FREQ_CTRL_ERROR_FAIL;
@@ -62,5 +62,5 @@ int determine_i2c_client(struct clock_cleaner *clockcleaner_info)
6262
goto i2c_client_ret;
6363
}
6464
i2c_client_ret:
65-
return ret;
65+
return ret;
6666
}

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_common_i2c.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,4 +13,4 @@
1313
struct clock_cleaner;
1414
int determine_i2c_client(struct clock_cleaner *);
1515

16-
#endif
16+
#endif

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_common_spi.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
*
88
*/
99

10-
#include "../intel_freq_control.h"
11-
#include "intel_freq_ctrl_common_spi.h"
10+
#include "../intel_freq_control.h"
11+
#include "intel_freq_ctrl_common_spi.h"
1212

1313
static int spi_dev_check(struct device *dev, void *data)
1414
{

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_common_spi.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,14 @@
44
* Author(s):
55
*/
66

7-
#ifndef HAVE_INTEL_FREQ_CONTROL_COMMON_SPI_H
8-
#define HAVE_INTEL_FREQ_CONTROL_COMMON_SPI_H
7+
#ifndef HAVE_INTEL_FREQ_CONTROL_COMMON_SPI_H
8+
#define HAVE_INTEL_FREQ_CONTROL_COMMON_SPI_H
99

10-
#define INTEL_FPGA_SPI_ERROR 0
11-
#define INTEL_FPGA_SPI_SUCCESS 1
10+
#define INTEL_FPGA_SPI_ERROR 0
11+
#define INTEL_FPGA_SPI_SUCCESS 1
1212

1313
struct clock_cleaner;
1414
int determine_spi_client(struct clock_cleaner *cc);
1515
u8 spi_msg_transfer(struct spi_device *spi, void *tx_buf, void *rx_buf);
1616

17-
#endif
17+
#endif

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_zl30733.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,11 @@
66
* Lubana Badakar <[email protected]>
77
*/
88

9-
#ifndef HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_H
10-
#define HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_H
11-
9+
#ifndef HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_H
10+
#define HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_H
1211

1312
int zl30733_sysfs_configure(struct i2c_client *i2c_cli);
1413
u8 i2c_zl30733_write_byte_data(const struct i2c_client *client, u16 reg, u8 data[], u8 data_len);
1514
u8 i2c_zl30733_read_byte_data(const struct i2c_client *client, u16 reg, u8 *buf, u8 data_len);
1615

17-
#endif //HAVE_INTEL_FREQUENCY_CONTROL_ZL30793_H
16+
#endif //HAVE_INTEL_FREQUENCY_CONTROL_ZL30793_H

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_zl30733_debugfs.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,15 @@
88
*
99
*/
1010

11-
#include <linux/delay.h>
12-
#include <linux/init.h>
13-
#include <linux/i2c-dev.h>
14-
#include <linux/i2c.h>
15-
#include <linux/kernel.h>
16-
#include <linux/debugfs.h>
17-
#include "../intel_freq_control.h"
18-
#include "intel_freq_ctrl_zl30733_i2c.h"
19-
#include "intel_freq_ctrl_zl30733_debugfs.h"
11+
#include <linux/delay.h>
12+
#include <linux/init.h>
13+
#include <linux/i2c-dev.h>
14+
#include <linux/i2c.h>
15+
#include <linux/kernel.h>
16+
#include <linux/debugfs.h>
17+
#include "../intel_freq_control.h"
18+
#include "intel_freq_ctrl_zl30733_i2c.h"
19+
#include "intel_freq_ctrl_zl30733_debugfs.h"
2020

2121
/* Register Map Page 0, General */
2222
u16 zl30733_reg_page_0[] = {
@@ -545,7 +545,7 @@ struct zarlink_pll_dbg {
545545
u32 readaddr;
546546
};
547547

548-
#define BUF_SIZE 8192U
548+
#define BUF_SIZE 8192U
549549

550550
static ssize_t zl30733_dpll_manual_freq_offset_show(struct file *filep, char __user *ubuf,
551551
size_t count, loff_t *offp)

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_zl30733_debugfs.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,9 @@
66
* Inian Pavel <[email protected]>
77
*/
88

9-
#ifndef HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_DEBUGFS_H
10-
#define HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_DEBUGFS_H
9+
#ifndef HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_DEBUGFS_H
10+
#define HAVE_INTEL_FREQUENCY_CONTROL_ZL30733_DEBUGFS_H
1111

1212
struct zarlink_pll_dbg *zl30733_dbgfs_init(struct i2c_client *i2c_cli);
1313
void zl30733_dbgfs_remove(struct zarlink_pll_dbg *d);
14-
#endif //HAVE_INTEL_FREQUENCY_CONTROL_ZL30793_DEBUGFS_H
14+
#endif //HAVE_INTEL_FREQUENCY_CONTROL_ZL30793_DEBUGFS_H

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_zl30733_i2c.c‎

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,17 @@
88
*
99
*/
1010

11-
#include <linux/init.h>
12-
#include <linux/i2c-dev.h>
13-
#include <linux/i2c.h>
14-
#include <linux/kernel.h>
15-
#include <linux/math64.h>
16-
#include <linux/module.h>
17-
#include <linux/workqueue.h>
18-
#include <linux/spi/spi.h>
19-
#include "../intel_freq_control.h"
20-
#include "intel_freq_ctrl_zl30733_debugfs.h"
21-
#include "intel_freq_ctrl_zl30733_i2c.h"
11+
#include <linux/init.h>
12+
#include <linux/i2c-dev.h>
13+
#include <linux/i2c.h>
14+
#include <linux/kernel.h>
15+
#include <linux/math64.h>
16+
#include <linux/module.h>
17+
#include <linux/workqueue.h>
18+
#include <linux/spi/spi.h>
19+
#include "../intel_freq_control.h"
20+
#include "intel_freq_ctrl_zl30733_debugfs.h"
21+
#include "intel_freq_ctrl_zl30733_i2c.h"
2222

2323
u8 i2c_zl30733_write_byte_data(const struct i2c_client *client, u16 reg, u8 data[], u8 data_len)
2424
{
@@ -250,7 +250,6 @@ static void pll_lock_handler(struct work_struct *work)
250250
}
251251
}
252252

253-
254253
int i2c_dev_check_zl30733_clock(struct intel_freq_control_private *priv)
255254
{
256255
struct i2c_client *i2c_cli = NULL;
@@ -267,14 +266,13 @@ int i2c_dev_check_zl30733_clock(struct intel_freq_control_private *priv)
267266
rdbuf[0], rdbuf[1]);
268267

269268
if (((rdbuf[0] << 8) | rdbuf[1]) == ZL30733_ID_VALUE) {
270-
#ifdef CONFIG_DEBUG_FS
269+
#ifdef CONFIG_DEBUG_FS
271270
zl30733_dbgfs_init(i2c_cli);
272-
#endif
271+
#endif
273272
priv->pll_lock_check_ctr = 0;
274273
INIT_DELAYED_WORK(&priv->pll_lock_dwork, pll_lock_handler);
275274
schedule_delayed_work(&priv->pll_lock_dwork,
276275
msecs_to_jiffies(1));
277-
278276
}
279277
}
280278

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_zl30733_i2c.h‎

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -7,70 +7,70 @@
77
* Inian Pavel Sakthi <[email protected]>
88
*/
99

10-
#ifndef HAVE_INTEL_FREQ_CONTROL_ZL30733_I2C_H
11-
#define HAVE_INTEL_FREQ_CONTROL_ZL30733_I2C_H
10+
#ifndef HAVE_INTEL_FREQ_CONTROL_ZL30733_I2C_H
11+
#define HAVE_INTEL_FREQ_CONTROL_ZL30733_I2C_H
1212
// Register numbers and other defines for ZL30733
13-
#define ZL30733_ADDR_TO_PAGE(addr) (((addr) & 0xf80) >> 7)
14-
#define ZL30733_ADDR_ADDR(addr) ((addr) & 0x7f)
15-
#define ZL30733_ID_VALUE 0x0e95 // ZL30733
16-
#define ZL30733_REG_ID_0 0x0001
17-
#define ZL30733_REG_ID_1 0x0002
18-
#define ZL30733_REG_PAGE_SEL 0x007f
19-
#define ZL30733_REG_DPLL_MON_STATUS(x) (0x0110 + (x)) // x=0-7
20-
#define ZL30733_REG_DPLL_MODE_REFSEL_0 0x0284
21-
#define ZL30733_REG_DPLL_CTRL_0 0x0285
13+
#define ZL30733_ADDR_TO_PAGE(addr) (((addr) & 0xf80) >> 7)
14+
#define ZL30733_ADDR_ADDR(addr) ((addr) & 0x7f)
15+
#define ZL30733_ID_VALUE 0x0e95 // ZL30733
16+
#define ZL30733_REG_ID_0 0x0001
17+
#define ZL30733_REG_ID_1 0x0002
18+
#define ZL30733_REG_PAGE_SEL 0x007f
19+
#define ZL30733_REG_DPLL_MON_STATUS(x) (0x0110 + (x)) // x=0-7
20+
#define ZL30733_REG_DPLL_MODE_REFSEL_0 0x0284
21+
#define ZL30733_REG_DPLL_CTRL_0 0x0285
2222

23-
#define ZL30733_REG_DPLL_DF_OFFSET_0_0 0x0300 // bit 47:40
24-
#define ZL30733_REG_DPLL_DF_OFFSET_0_1 0x0301 // bit 39:32
25-
#define ZL30733_REG_DPLL_DF_OFFSET_0_2 0x0302 // bit 31:24
26-
#define ZL30733_REG_DPLL_DF_OFFSET_0_3 0x0303 // bit 23:16
27-
#define ZL30733_REG_DPLL_DF_OFFSET_0_4 0x0304 // bit 15:8
28-
#define ZL30733_REG_DPLL_DF_OFFSET_0_5 0x0305 // bit 7:0
23+
#define ZL30733_REG_DPLL_DF_OFFSET_0_0 0x0300 // bit 47:40
24+
#define ZL30733_REG_DPLL_DF_OFFSET_0_1 0x0301 // bit 39:32
25+
#define ZL30733_REG_DPLL_DF_OFFSET_0_2 0x0302 // bit 31:24
26+
#define ZL30733_REG_DPLL_DF_OFFSET_0_3 0x0303 // bit 23:16
27+
#define ZL30733_REG_DPLL_DF_OFFSET_0_4 0x0304 // bit 15:8
28+
#define ZL30733_REG_DPLL_DF_OFFSET_0_5 0x0305 // bit 7:0
2929

3030
/* bit 15:8 :0x0001 bit 7:0 :0x0002 */
31-
#define ZL30733_PAGE0_REG_GENERAL_ID_0 0x0001
31+
#define ZL30733_PAGE0_REG_GENERAL_ID_0 0x0001
3232
/* bit 2:0 state [0: FREERUN (or NCO mode) 1: HOLDOVER
3333
* 2: FAST_LOCK 3: ACQUIRING 4: LOCK]
3434
*/
35-
#define ZL30733_PAGE2_REG_DPLL_STATE_OFFSET_0 0x0120
35+
#define ZL30733_PAGE2_REG_DPLL_STATE_OFFSET_0 0x0120
3636

37-
#define ZL30733_PAGE2_REG_DPLL_STATE_OFFSET_1 0x0121
37+
#define ZL30733_PAGE2_REG_DPLL_STATE_OFFSET_1 0x0121
3838
/* bit 2:0 mode */
39-
#define ZL30733_PAGE4_REG_DPLL_MODE_REFSEL_0 0x0284
39+
#define ZL30733_PAGE4_REG_DPLL_MODE_REFSEL_0 0x0284
4040

41-
#define ZL30733_PAGE4_REG_DPLL_MODE_REFSEL_1 0x0288
41+
#define ZL30733_PAGE4_REG_DPLL_MODE_REFSEL_1 0x0288
4242

4343
/* bit 4:ignore sync bit 3:nco_hybrid_en bit 2:nco_auto_read
4444
* bit 1:tod_step_reset bit 0:tie_clear
4545
*/
46-
#define ZL30733_PAGE4_REG_DPLL_CTRL_0 0x0285
47-
#define ZL30733_PAGE4_REG_DPLL_CTRL_1 0x0289
46+
#define ZL30733_PAGE4_REG_DPLL_CTRL_0 0x0285
47+
#define ZL30733_PAGE4_REG_DPLL_CTRL_1 0x0289
4848
/* bit 47:40 :0x300 bit 39:32 :0x301 bit 31:24 :0x302
4949
* bit 23:16 :0x303 bit 15:8 :0x304 bit 7:0 :0x305
5050
*/
51-
#define ZL30733_PAGE6_REG_DPLL_DF_OFFSET_0_0 0x0300
51+
#define ZL30733_PAGE6_REG_DPLL_DF_OFFSET_0_0 0x0300
5252
/* 7:0 :0x306, bit 4 read_sem */
53-
#define ZL30733_PAGE5_REG_DPLL_DF_READ_0 0x02A8
53+
#define ZL30733_PAGE5_REG_DPLL_DF_READ_0 0x02A8
5454

55-
#define ZL30733_PAGE5_REG_DPLL_DF_READ_1 0x02A9
55+
#define ZL30733_PAGE5_REG_DPLL_DF_READ_1 0x02A9
5656

57-
#define ZL30733_REG_DPLL_MODE_REFSEL_0 0x0284
57+
#define ZL30733_REG_DPLL_MODE_REFSEL_0 0x0284
5858

59-
#define ZL30733_REG_READ_INTERVAL (10)
60-
#define ZL30733_DPLL_DF_CTRL_SEM_GET(data) (((data) & 0x10) >> 4)
61-
#define ZL30733_DPLL_NCO_MODE 0x04
62-
#define ZL30733_DPLL_MODE_MASK 0x07
63-
#define ZL30733_DPLL_CHECK_NCO_MODE(x) (((x) & ZL30733_DPLL_MODE_MASK) == ZL30733_DPLL_NCO_MODE)
64-
#define ZL30733_DPLL_SET_NCO_MODE(x) (((x) & 0xf8) | ZL30733_DPLL_NCO_MODE)
59+
#define ZL30733_REG_READ_INTERVAL (10)
60+
#define ZL30733_DPLL_DF_CTRL_SEM_GET(data) (((data) & 0x10) >> 4)
61+
#define ZL30733_DPLL_NCO_MODE 0x04
62+
#define ZL30733_DPLL_MODE_MASK 0x07
63+
#define ZL30733_DPLL_CHECK_NCO_MODE(x) (((x) & ZL30733_DPLL_MODE_MASK) == ZL30733_DPLL_NCO_MODE)
64+
#define ZL30733_DPLL_SET_NCO_MODE(x) (((x) & 0xf8) | ZL30733_DPLL_NCO_MODE)
6565

66-
#define ZL30733_LOCK_CHECK_INTERVAL_IN_MS (500)
67-
#define ZL30733_DPLL_IS_LOCKED(data) ((data) & 0x01)
68-
#define ZL30733_MAX_PLL_LOCK_CHECK_COUNTER (200)
66+
#define ZL30733_LOCK_CHECK_INTERVAL_IN_MS (500)
67+
#define ZL30733_DPLL_IS_LOCKED(data) ((data) & 0x01)
68+
#define ZL30733_MAX_PLL_LOCK_CHECK_COUNTER (200)
6969
int i2c_dev_check_zl30733_clock(struct intel_freq_control_private *priv);
7070

7171
void intel_freq_control_zl30733(struct work_struct *work);
7272

7373
u8 i2c_zl30733_write_byte_data(const struct i2c_client *client, u16 reg, u8 data[], u8 data_len);
7474
u8 i2c_zl30733_read_byte_data(const struct i2c_client *client, u16 reg, u8 *buf, u8 data_len);
7575

76-
#endif
76+
#endif

‎drivers/net/ethernet/altera/dpll/intel_freq_ctrl_zl30793.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -6,16 +6,16 @@
66
* Lubana Badakar <[email protected]>
77
*/
88

9-
#include <linux/delay.h>
10-
#include <linux/init.h>
11-
#include <linux/i2c-dev.h>
12-
#include <linux/i2c.h>
13-
#include <linux/kernel.h>
14-
#include <linux/math64.h>
15-
#include <linux/module.h>
16-
#include <linux/workqueue.h>
17-
#include <linux/spi/spi.h>
18-
#include "intel_freq_ctrl_zl30793.h"
9+
#include <linux/delay.h>
10+
#include <linux/init.h>
11+
#include <linux/i2c-dev.h>
12+
#include <linux/i2c.h>
13+
#include <linux/kernel.h>
14+
#include <linux/math64.h>
15+
#include <linux/module.h>
16+
#include <linux/workqueue.h>
17+
#include <linux/spi/spi.h>
18+
#include "intel_freq_ctrl_zl30793.h"
1919

2020
/* Register Map Page 0, General */
2121
u16 zl30793_reg_page_0[] = {
@@ -478,7 +478,7 @@ static DEVICE_ATTR(zl30793_dpll_manual_freq_offset, 0644,
478478
zl30793_dpll_manual_freq_offset_show,
479479
zl30793_dpll_manual_freq_offset_store);
480480

481-
static DEVICE_ATTR(zl30793_reg_dump, 0444, zl30793_reg_dump_show, NULL);
481+
static DEVICE_ATTR_RO(zl30793_reg_dump);
482482

483483
static struct attribute *zl30793_sysfs_attrs[] = {
484484
&dev_attr_zl30793_dpll_manual_freq_offset.attr,

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