Correct Default SPL_SIZE_LIMIT for Cyclone/Arria V#19
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TCWORLD wants to merge 1 commit intoaltera-fpga:socfpga_v2024.01from
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Correct Default SPL_SIZE_LIMIT for Cyclone/Arria V#19TCWORLD wants to merge 1 commit intoaltera-fpga:socfpga_v2024.01from
TCWORLD wants to merge 1 commit intoaltera-fpga:socfpga_v2024.01from
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Refer to the Cyclone V Hard Processor System Technical Reference Manual (same for Arria V), Section A-32, "Loading the Preloader Image". The upper 4kB of the on-chip RAM is reserved by the Boot ROM, meaning only 60kB is available for the preloader. If the SPL extends into this region, it causes the boot ROM to crash.
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Thanks for this patch that helped me understand why I was not able to boot anymore when upgrading uboot from 2022.07 to 2025.01 on a Terasic DE10-Standard board. My generated SPL was now slightly bigger than the limit. I don't understand why this simple fix is not merged yet. |
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Refer to the Cyclone V Hard Processor System Technical Reference Manual (same for Arria V), Section A-32, "Loading the Preloader Image". The upper 4kB of the on-chip RAM is reserved by the Boot ROM, meaning only 60kB is available for the preloader. If the SPL extends into this region, it causes the boot ROM to crash.
Proper validation will prevent confusion when the preloader doesn't run due to being too large.