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4 changes: 2 additions & 2 deletions amaranth/back/rtlil.py
Original file line number Diff line number Diff line change
Expand Up @@ -383,13 +383,13 @@ def emit_signal_wires(self):
if name in self.module.ports:
port_value, _flow = self.module.ports[name]
assert value == port_value
self.name_map[signal] = (*self.module.name, f"\\{name}")
self.name_map[signal] = (*self.module.name, name)
else:
wire = self.builder.wire(width=signal.width, signed=signal.signed,
name=name, attrs=attrs,
src=_src(signal.src_loc))
self.sigport_wires[name] = (wire, value)
self.name_map[signal] = (*self.module.name, wire)
self.name_map[signal] = (*self.module.name, wire[1:])

def emit_port_wires(self):
named_signals = {name: signal for signal, name in self.module.signal_names.items()}
Expand Down