Ensure all allowed filter bit combinations can be set on on AD7124.#36
Open
robste1987 wants to merge 1 commit intoanalogdevicesinc:masterfrom
Open
Ensure all allowed filter bit combinations can be set on on AD7124.#36robste1987 wants to merge 1 commit intoanalogdevicesinc:masterfrom
robste1987 wants to merge 1 commit intoanalogdevicesinc:masterfrom
Conversation
If the parameter of AD7124_FILT_REG_FS() was changed from 384, it was unlikely to be transferred to the AD7124 properly. This made it impossible to change the output data rate of the ADC. Root cause is that all filter registers have a Power-On/Reset Value of 0x060180, which means that FS is 0x180 (=384) by default. Instead of replacing the default value by the paramter of AD7124_FILT_REG_FS(), the default value and the paramter were binary anded and the result was written into the FS bits. Solution is to build up the new register content from 0. It ensures the default POST_FILTER setting is kept if not expilicitly changed. The REJ60 and SINGLE_CYCLE bits stay clear as they are in Power-On/Reset. This is considered okay because this code is intended to initialize the AD7124 after a power-on or reset.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
If the parameter of AD7124_FILT_REG_FS() was changed from 384, it was unlikely to be transferred to the AD7124 properly. This made it impossible to change the output data rate of the ADC.
Root cause is that all filter registers have a Power-On/Reset Value of 0x060180, which means that FS is 0x180 (=384) by default. Instead of replacing the default value by the paramter of AD7124_FILT_REG_FS(), the default value and the paramter were binary anded and the result was written into the FS bits.
Solution is to build up the new register content from 0. It ensures the default POST_FILTER setting is kept if not expilicitly changed. The REJ60 and SINGLE_CYCLE bits stay clear as they are in Power-On/Reset. This is considered okay because this code is intended to initialize the AD7124 after a power-on or reset.