ADSP-SC598 upstream driver changes v2 #3083
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Add headers for GPIO port management, RCU and general system configuration Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Co-developed-by: Utsav Agarwal <[email protected]> Signed-off-by: Utsav Agarwal <[email protected]> Co-developed-by: Arturs Artamonovs <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Support triggering a software reset Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Co-developed-by: Utsav Agarwal <[email protected]> Signed-off-by: Utsav Agarwal <[email protected]> Co-developed-by: Arturs Artamonovs <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add bindings for the reset controller in ADI ADSP-SC5xx SoCs Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Co-developed-by: Utsav Agarwal <[email protected]> Signed-off-by: Utsav Agarwal <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add bindings for ADI evaluation boards using ADSP-SC59x SoCs Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Co-developed-by: Utsav Agarwal <[email protected]> Signed-off-by: Utsav Agarwal <[email protected]> Co-developed-by: Arturs Artamonovs <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Implement the clock tree without dynamic PLL rate change Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add device tree bindings for the ADSP-SC5xx clock distribution unit (CDU) and clock generation unit (CGU) Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add ADSP-SC5xx clock driver Co-developed-by: Arturs Artamonovs <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Co-developed-by: Utsav Agarwal <[email protected]> Signed-off-by: Utsav Agarwal <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add bindings for the ADSP-SC5xx pinmux control Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Support switching GPIO pin functions Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
- Support FIFO mode - Support earlyprintk - Support Enable Divide By One support, for higher clock resolutions. Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add bindings for the ADSP-SC5xx UART Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add support for the ADSP-SC59x SoC, EV-SC598-SOM and EV-SOMCRR-EZKIT Co-developed-by: Nathan Barrett-Morrison <[email protected]> Signed-off-by: Nathan Barrett-Morrison <[email protected]> Co-developed-by: Greg Malysa <[email protected]> Signed-off-by: Greg Malysa <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add Arturs Artamonov as the maintainer of ADSP-SC5xx SoCs Signed-off-by: Arturs Artamonovs <[email protected]> Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
Add initial support for the ADSP-SC598 Signed-off-by: Philip Molloy <[email protected]> Signed-off-by: Arturs Artamonovs <[email protected]>
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PR Description
Set of patches for v2 upstream submission
PR Type
PR Checklist