Backport AD7768-1 driver from upstream tree

Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml

@@ -4,18 +4,26 @@
 $id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Analog Devices AD7768-1 ADC device driver
+title: Analog Devices AD7768-1 ADC family
 
 maintainers:
   - Michael Hennerich <michael.hennerich@analog.com>
 
 description: |
-  Datasheet at:
-    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+  Analog Devices AD7768-1 24-Bit Single Channel Low Power sigma-delta ADC family
+
+  https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+  https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7767-1.pdf
+  https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7768-1.pdf
+  https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7769-1.pdf
 
 properties:
   compatible:
-    const: adi,ad7768-1
+    enum:
+      - adi,ad7768-1
+      - adi,adaq7767-1
+      - adi,adaq7768-1
+      - adi,adaq7769-1
 
   reg:
     maxItems: 1
@@ -26,7 +34,26 @@ properties:
   clock-names:
     const: mclk
 
+  trigger-sources:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 2
+    description: |
+      A list of phandles referencing trigger source providers. Each entry
+      represents a trigger source for the ADC:
+
+        - First entry specifies the device responsible for driving the
+          synchronization (SYNC_IN) pin, as an alternative to adi,sync-in-gpios.
+          This can be a `gpio-trigger` or another `ad7768-1` device. If the
+          device's own SYNC_OUT pin is internally connected to its SYNC_IN pin,
+          reference the device itself or omit this property.
+        - Second entry optionally defines a GPIO3 pin used as a START signal trigger.
+
+      Use the accompanying trigger source cell to identify the type of each entry.
+
   interrupts:
+    description:
+      DRDY (Data Ready) pin, which signals conversion results are available.
     maxItems: 1
 
   '#address-cells':
@@ -39,6 +66,25 @@ properties:
     description:
       ADC reference voltage supply
 
+  adi,aaf-gain-bp:
+    description: |
+       Specifies the gain applied by the Analog Anti-Aliasing Filter (AAF)
+       to the ADC input in basis points (one hundredth of a percent).
+       The hardware gain is determined by which input pin(s) the signal goes
+       through into the AAF. The possible connections are:
+       * For the ADAQ7767-1: Input connected to IN1±, IN2± or IN3±.
+       * For the ADAQ7769-1: OUT_PGA pin connected to IN1_AAF+, IN2_AAF+,
+         or IN3_AAF+.
+    enum: [1430, 3640, 10000]
+    default: 10000
+
+  pga-gpios:
+    description:
+      GAIN 0, GAIN1 and GAIN2 pins for gain selection. For devices that have
+      PGA configuration input pins, pga-gpios must be defined.
+    minItems: 3
+    maxItems: 3
+
   adi,sync-in-gpios:
     maxItems: 1
     description:
@@ -47,6 +93,19 @@ properties:
       in any way, for example if the filter decimation rate changes.
       As the line is active low, it should be marked GPIO_ACTIVE_LOW.
 
+  regulators:
+    type: object
+    description:
+      list of regulators provided by this controller.
+
+    properties:
+      vcm-output:
+        $ref: /schemas/regulator/regulator.yaml#
+        type: object
+        unevaluatedProperties: false
+
+    additionalProperties: false
+
   reset-gpios:
     maxItems: 1
 
@@ -57,6 +116,23 @@ properties:
   "#io-channel-cells":
     const: 1
 
+  "#trigger-source-cells":
+    description: |
+      Cell indicates the trigger output signal: 0 = SYNC_OUT, 1 = GPIO3,
+      2 = DRDY.
+
+      For better readability, macros for these values are available in
+      dt-bindings/iio/adc/adi,ad7768-1.h.
+    const: 1
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+    description: |
+      The first cell is for the GPIO number: 0 to 3.
+      The second cell takes standard GPIO flags.
+
 required:
   - compatible
   - reg
@@ -65,7 +141,16 @@ required:
   - vref-supply
   - spi-cpol
   - spi-cpha
-  - adi,sync-in-gpios
+
+dependencies:
+  adi,sync-in-gpios:
+    not:
+      required:
+        - trigger-sources
+  trigger-sources:
+    not:
+      required:
+        - adi,sync-in-gpios
 
 patternProperties:
   "^channel@([0-9]|1[0-5])$":
@@ -89,6 +174,35 @@ patternProperties:
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
 
+  # AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,adaq7767-1
+              - adi,adaq7769-1
+    then:
+      required:
+        - adi,aaf-gain-bp
+    else:
+      properties:
+        adi,aaf-gain-bp: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,adaq7768-1
+              - adi,adaq7769-1
+    then:
+      required:
+        - pga-gpios
+    else:
+      properties:
+        pga-gpios: false
+
 unevaluatedProperties: false
 
 examples:
@@ -105,6 +219,8 @@ examples:
             spi-max-frequency = <2000000>;
             spi-cpol;
             spi-cpha;
+            gpio-controller;
+            #gpio-cells = <2>;
             vref-supply = <&adc_vref>;
             interrupts = <25 IRQ_TYPE_EDGE_RISING>;
             interrupt-parent = <&gpio>;
@@ -120,6 +236,12 @@ examples:
                 reg = <0>;
                 label = "channel_0";
             };
+
+            regulators {
+              vcm_reg: vcm-output {
+                regulator-name = "ad7768-1-vcm";
+              };
+            };
         };
     };
 ...

MAINTAINERS

@@ -1429,6 +1429,7 @@ S:	Supported
 W:	https://ez.analog.com/linux-software-drivers
 F:	Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
 F:	drivers/iio/adc/ad7768-1.c
+F:	include/dt-bindings/iio/adc/adi,ad7768-1.h
 
 ANALOG DEVICES INC AD7780 DRIVER
 M:	Michael Hennerich <Michael.Hennerich@analog.com>

arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10_nano_cn0540.dts

@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
+#include <dt-bindings/iio/adc/adi,ad7768-1.h>
 
 / {
 	vref: regulator-vref {
@@ -98,14 +99,18 @@
 	};
 
 	spi@30000 {
-		compatible = "adi,legacy-axi-spi-engine-1.00.a";
+		compatible = "adi,axi-spi-engine-1.00.a";
 		reg = <0x00030000 0x00010000>;
 		interrupt-parent = <&intc>;
 		interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&sys_clk &h2f_user0_clk>;
 		clock-names = "s_axi_aclk", "spi_clk";
 		num-cs = <1>;
 
+		trigger-sources = <&ad7768_1 AD7768_TRIGGER_SOURCE_DRDY>;
+		dmas = <&axi_dmac_0 0>;
+		dma-names = "offload0-rx";
+
 		#address-cells = <0x1>;
 		#size-cells = <0x0>;
 
@@ -117,14 +122,28 @@
 			spi-cpha;
 			#gpio-cells = <2>;
 			gpio-controller;
+			interrupts = <0 46 IRQ_TYPE_EDGE_RISING>;
+			interrupt-parent = <&intc>;
 			vref-supply = <&vref>;
 			adi,sync-in-gpios = <&gpio_out 1 GPIO_ACTIVE_LOW>;
 			reset-gpios = <&gpio_out 0 GPIO_ACTIVE_LOW>;
 			clocks = <&ad7768_1_mclk>;
 			clock-names = "mclk";
-			dmas = <&axi_dmac_0 0>;
-			dma-names = "rx";
+			#trigger-source-cells = <1>;
 			#io-channel-cells = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			regulators {
+				vcm_reg: vcm-output {
+					regulator-name = "ad7768-1-vcm";
+				};
+			};
+
+			channel@0 {
+				reg = <0>;
+				label = "channel_0";
+			};
 		};
 	};
 };

arch/arm/boot/dts/xilinx/zynq-coraz7s-cn0540.dts

@@ -17,6 +17,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
+#include <dt-bindings/iio/adc/adi,ad7768-1.h>
+
 / {
 	vref: regulator-vref {
 		compatible = "regulator-fixed";
@@ -27,58 +29,58 @@
 	};
 
 	clocks {
 		ad7768_1_mclk: clock@0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <16384000>;
 		};
 	};
 
 	one-bit-adc-dac@0 {
 		compatible = "adi,one-bit-adc-dac";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		in-gpios =  <&gpio0 91 GPIO_ACTIVE_HIGH>;
 		out-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH>,
 			    <&gpio0 89 GPIO_ACTIVE_HIGH>,
 			    <&gpio0 94 GPIO_ACTIVE_HIGH>,
 			    <&ad7768_1 0 GPIO_ACTIVE_HIGH>,
 			    <&ad7768_1 1 GPIO_ACTIVE_HIGH>,
 			    <&ad7768_1 2 GPIO_ACTIVE_HIGH>,
 			    <&ad7768_1 3 GPIO_ACTIVE_HIGH>;
 		channel@0 {
 			reg = <0>;
 			label = "cn0540_sw_ff_gpio";
 		};
 		channel@1 {
 			reg = <1>;
 			label = "cn0540_red_led";
 		};
 		channel@2 {
 			reg = <2>;
 			label = "cn0540_blue_led";
 		};
 		channel@3 {
 			reg = <3>;
 			label = "cn0540_shutdown_gpio";
 		};
 		channel@4 {
 			reg = <4>;
 			label = "cn0540_ad7768-1-gpio0";
 		};
 		channel@5 {
 			reg = <5>;
 			label = "cn0540_ad7768-1-gpio1";
 		};
 		channel@6 {
 			reg = <6>;
 			label = "cn0540_FDA_DIS";
 		};
 		channel@7 {
 			reg = <7>;
 			label = "cn0540_FDA_MODE";
 		};
 	};
 };
 
 &adc {
@@ -120,14 +122,18 @@
 	};
 
 	axi_spi_engine_0: spi@44a00000 {
-		compatible = "adi,legacy-axi-spi-engine-1.00.a";
+		compatible = "adi,axi-spi-engine-1.00.a";
 		reg = <0x44a00000 0x10000>;
 		interrupt-parent = <&intc>;
 		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc 15 &spi_clk>;
 		clock-names = "s_axi_aclk", "spi_clk";
 		num-cs = <1>;
 
+		trigger-sources = <&ad7768_1 AD7768_TRIGGER_SOURCE_DRDY>;
+		dmas = <&rx_dma 0>;
+		dma-names = "offload0-rx";
+
 		#address-cells = <0x1>;
 		#size-cells = <0x0>;
 
@@ -140,13 +146,27 @@
 			vref-supply = <&vref>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			interrupts = <99 IRQ_TYPE_EDGE_RISING>;
+			interrupt-parent = <&gpio0>;
 			adi,sync-in-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
 			reset-gpios = <&gpio0 93 GPIO_ACTIVE_LOW>;
 			clocks = <&ad7768_1_mclk>;
 			clock-names = "mclk";
-			dmas = <&rx_dma 0>;
-			dma-names = "rx";
+			#trigger-source-cells = <1>;
 			#io-channel-cells = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			regulators {
+				vcm_reg: vcm-output {
+					regulator-name = "ad7768-1-vcm";
+				};
+			};
+
+			channel@0 {
+				reg = <0>;
+				label = "channel_0";
+			};
 		};
 	};