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arm/arm64: dts: adi: sc59x: fix I2C and CRC nodes #3209

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arm/arm64: dts: adi: sc59x: fix I2C and CRC nodes #3209

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163a4fe
arm: dts: adi: sc59x: fix CRC nodes
jiez Mar 25, 2026
8563629
arm64: dts: adi: fix CRC nodes for sc59x-64
jiez Mar 25, 2026
404c94d
arm: dts: adi: sc59x: fix I2C nodes
jiez Mar 25, 2026
f1c2c1d
arm64: dts: adi: remove useless code
jiez Mar 25, 2026
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16 changes: 0 additions & 16 deletions arch/arm/boot/dts/adi/sc594-som.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -184,58 +184,50 @@

status = "disabled";

flash0: is25lx256@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "is25lx256", "jedec,spi-nor";
reg = <0>;

spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <125000000>;

cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <255>;
cdns,tchsh-ns = <8>;
cdns,tslch-ns = <8>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

ospi_0: partition@0 {
label = "u-boot-spl";
reg = <0x0 0x40000>;
};

ospi_1: partition@1 {
label = "u-boot";
reg = <0x40000 0xc0000>;
};

ospi_2: partition@3 {
label = "kernel";
reg = <0x100000 0xf00000>;
};

ospi_3: partition@4 {
label = "rootfs";
reg = <0x01000000 0x1000000>;
};
};
};

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(avoid_unnecessary_addr_size): /scb/spi@31027000/is25lx256@0: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property
};

&i2c0 {
status = "disabled";
};

&i2c1 {
status = "disabled";
};

&i2c2 {
status = "okay";

Expand Down Expand Up @@ -303,14 +295,6 @@
};
};

&crc0 {
status = "disabled";
};

&crc1 {
status = "disabled";
};

&usb0_phy {
reset-gpios = <&gpg 11 GPIO_ACTIVE_LOW>;
status = "okay";
Expand Down Expand Up @@ -460,16 +444,16 @@
};

&tru {
rpmsg_to_a55: channel@0 {
adi,tru-master-id = <139>; /* trigger master SOFT3 */
adi,tru-slave-id = <160>; /* TRU0_IRQ3 */
};

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(unit_address_vs_reg): /scb/tru@3108A000/channel@0: node has a unit name, but no reg or ranges property
rpmsg_to_sharc0: channel@1 {
adi,tru-master-id = <140>; /* trigger master SOFT4 */
adi,tru-slave-id = <164>; /* TRU0_IRQ7 */
};

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(unit_address_vs_reg): /scb/tru@3108A000/channel@1: node has a unit name, but no reg or ranges property
rpmsg_to_sharc1: channel@2 {
adi,tru-master-id = <141>; /* trigger master SOFT5 */
adi,tru-slave-id = <168>; /* TRU0_IRQ11 */
};

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(unit_address_vs_reg): /scb/tru@3108A000/channel@2: node has a unit name, but no reg or ranges property
};
75 changes: 66 additions & 9 deletions arch/arm/boot/dts/adi/sc59x.dtsi
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Expand Up @@ -44,6 +44,9 @@
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2s4 = &i2s4;
mmc0 = &mmc0;
sru0 = &sru_ctrl_dai0;
Expand Down Expand Up @@ -98,19 +101,19 @@
ranges = <0 0x20040000 0x40000>; /*256KiB*/
};

sys_clkin0: sys-clkin0@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "sys_clkin0";
};

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(unit_address_vs_reg): /sys-clkin0@1: node has a unit name, but no reg or ranges property

sys_clkin1: sys-clkin1@2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "sys_clkin1";
};

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(unit_address_vs_reg): /sys-clkin1@2: node has a unit name, but no reg or ranges property

clk: clocks@3108d000 {
compatible = "adi,sc594-clocks";
Expand Down Expand Up @@ -351,7 +354,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001400 0xFF>;
reg = <0x31001400 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
Expand All @@ -363,7 +366,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001500 0xFF>;
reg = <0x31001500 0x100>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
Expand All @@ -375,14 +378,50 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001600 0xFF>;
reg = <0x31001600 0x100>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};

i2c3: twi@31001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001000 0x100>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};

i2c4: twi@31001100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001100 0x100>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};

i2c5: twi@31001200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001200 0x100>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};

i2s4: i2s@4 {
compatible = "adi,sc5xx-i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
Expand Down Expand Up @@ -500,24 +539,42 @@
status = "disabled";
};

crc0: crc@31001200 {
crc0: crc@3100a500 {
compatible = "adi,hmac-crc";
reg = <0x31001200 0xFF>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x3100a500 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
dma_channel = <8>;
crypto_crc_poly = <0x5c5c5c5c>;
status = "disabled";
};

crc1: crc@31001300 {
crc1: crc@3100a600 {
compatible = "adi,hmac-crc";
reg = <0x31001300 0xFF>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x3100a600 0x100>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
dma_channel = <18>;
crypto_crc_poly = <0x5c5c5c5c>;
status = "disabled";
};

crc2: crc@3100aa00 {
compatible = "adi,hmac-crc";
reg = <0x3100aa00 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
dma_channel = <45>;
crypto_crc_poly = <0x5c5c5c5c>;
status = "disabled";
};

crc3: crc@3100ab00 {
compatible = "adi,hmac-crc";
reg = <0x3100ab00 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
dma_channel = <47>;
crypto_crc_poly = <0x5c5c5c5c>;
status = "disabled";
};

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@pamolloy pamolloy Mar 26, 2026 •
edited
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Please split the CRC changes into a separate commit. How did you come across the fact that the addresses were wrong and that there are two missing nodes? Is this the same in U-Boot? And where did you get the new interrupt numbers?

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@jiez jiez Mar 26, 2026

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Because 0x31001200 is the base address of i2c5. So crc0 cannot have the same base address. When looking for the correct address in the manuals, I noticed that sc59x has 4 CRC devices while sc57x and sc58x have only 2. U-Boot does not have CRC devices in sc5xx devicetree files. All information are from the latest processor hardware reference manuals.

pinctrl0: pinctrl@31004600 {
compatible = "adi,adsp-pinctrl";
#address-cells = <1>;
Expand Down Expand Up @@ -1087,60 +1144,60 @@
};
*/

spi_cluster: dma@3102D000 {
compatible = "adi,dma-controller";
reg = <0x3102D000 0x1000>;
status = "okay";
#dma-cells = <1>;

spi0_tx: channel@22 {
adi,id = <22>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0>;
};

spi0_rx: channel@23 {
adi,id = <23>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x80>;
};

spi1_tx: channel@24 {
adi,id = <24>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x100>;
};

spi1_rx: channel@25 {
adi,id = <25>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x180>;
};

spi2_tx: channel@26 {
adi,id = <26>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x200>;
};

spi2_rx: channel@27 {
adi,id = <27>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x280>;
};
};

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(simple_bus_reg): /scb/dma@3102D000: simple-bus unit address format error, expected "3102d000"

sport0_dma_cluster: dma@31022000 {
compatible = "adi,dma-controller";
Expand Down
8 changes: 0 additions & 8 deletions arch/arm64/boot/dts/adi/sc598-som.dtsi
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Expand Up @@ -204,14 +204,6 @@
cs-gpios = <&gpa 5 GPIO_ACTIVE_LOW>;
};

&i2c0 {
status = "okay";
};

&i2c1 {
status = "disabled";
};

&i2c2 {
status = "okay";
pinctrl-names = "default";
Expand Down
40 changes: 38 additions & 2 deletions arch/arm64/boot/dts/adi/sc59x-64.dtsi
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Expand Up @@ -574,7 +574,7 @@

crc0: crc@310a5000 {
compatible = "adi,hmac-crc";
reg = <0x310a5000 0xFF>;
reg = <0x310a5000 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&crc_cluster 8>;
dma-names = "mdma_chan";
Expand All @@ -584,14 +584,34 @@

crc1: crc@310a6000 {
compatible = "adi,hmac-crc";
reg = <0x310a6000 0xFF>;
reg = <0x310a6000 0x100>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&crc_cluster 18>;
dma-names = "mdma_chan";
crypto_crc_poly = <0x04C11DB7>;
status = "disabled";
};

crc2: crc@310aa000 {
compatible = "adi,hmac-crc";
reg = <0x310aa000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&crc_cluster 45>;
dma-names = "mdma_chan";
crypto_crc_poly = <0x04C11DB7>;
status = "disabled";
};

crc3: crc@310ab000 {
compatible = "adi,hmac-crc";
reg = <0x310ab000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&crc_cluster 47>;
dma-names = "mdma_chan";
crypto_crc_poly = <0x04C11DB7>;
status = "disabled";
};

pinctrl0: pinctrl@31004600 {
compatible = "adi,adsp-pinctrl";
#address-cells = <1>;
Expand Down Expand Up @@ -1198,6 +1218,22 @@
interrupt-names = "complete", "error";
adi,src-offset = <0x100>;
};

crc2_dma: channel@45 { /* MDMA4_SRC */
adi,id = <45>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x200>;
};

crc3_dma: channel@47 { /* MDMA5_SRC */
adi,id = <47>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x300>;
};
};

dma_cluster2: dma@31026000 {
Expand Down
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