Staging/rpi/ad9088 missing cherry picks#3216
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nunojsa merged 2 commits intorpi-6.12.yfrom Mar 27, 2026
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…0.1.3 Added: - API - Added support for AD9088 - API - Support for a new Profile format that consolidates and improves the data structures used by the part - this is a breaking change for Profile versions prior to V10. See Components Section below for Profile version - API - Integrated support for external trigger-based frequency hopping - API - New function to read part number with X-grade or B-grade and SW trim information (SW Trim 1/3/5) - FW - Allow ADC/DAC PN signal inversion based on user Profile settings Changed: - API - Some code cleanup and optimization by deleting unused code - API - Converted frequency representations from Hz to uHz (microhertz) throughout the ADF4030 driver and example code - this is a breaking change - FW - Upgrade device Profile. See Components Section below for Profile version - FW - For SerDes Rx, a number of bridging cal settings come from device Profile - FW - Device clock frequency variable changed from kHz to Hz - FW - Define the P-N inversion of the differential ADC/DAC RFIO in the device Profile - FW - 4D slice mode switching optimization - FW - Optimized receiver handling of overrange signal conditions Deprecated: - API - adi_apollo_clk_mcs_internal_sysref_per_set(), sync_logic_reset(), adi_apollo_jrx_subclass_set(), adi_apollo_clk_mcs_trig_reset_serdes_enable(), adi_apollo_adc_tlines_offset_set(), hsci_regio_rmw_write32() Fixed: - API - Bug fixed in adi_apollo_tmode_config_set(). Previously, the function ignored the resolution parameter and always set 16-bit resolution - API - Bug fixed in adi_apollo_cnco_profile_load() whereby an incorrect value could be written to the Profile when less than a full Profile array was being loaded - API - Bug fixed in tx_txpath_misc_configure() whereby register values were not updated - API - Increased delay after freezing of ADC background calibration before executing ADC slice mode switch within the slice mode switch prepare API function - FW - Bug fixed whereby MCS side-B was not being updated correctly during tracking calibration with dual clocking Errata: - API - ADF4030-FPGA Time-of-Flight measurement may time out when operating at low BSYNC frequencies - API - AD9084-SE ADC performance has not been fully optimized Supported: - AD9088 - AD9084 Components: - Device Driver API 2.0.10 - Firmware 2.0.6 - Device Profile 10.1.28 Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 92e2dca)
…le array OOB
Fix several 8T8R channel mapping bugs in the IIO channel-to-hardware
block mapping function:
1. TX/RX FDUC/FDDC logical-to-physical conversion: The xbar encoding
interleaves bands per channel (TXn*4 + BAND*2 + Q), but the mux
hardware uses physical numbering where all BAND0 come first (0-3)
then BAND1 (4-7). Convert using lookup table {0,4,1,5,2,6,3,7}.
Without this, TX fine NCOs target wrong hardware blocks and RX
channels only see a subset of CDDCs/ADCs.
2. TX mux0_sel lookup: mux0_sel[] is indexed by DAC number with the
value selecting a mod-switch output, not indexed by CDUC. For 8T8R,
the modsw mapping swaps CDUCs 1/2. Search mux0_sel[] for the
matching modsw output to find the correct DAC.
3. RX mux0_out_adc_sel indexing: The array is indexed by CB_OUT number,
not CDDC number. Add cddc_to_cbout[] translation for 8T8R.
4. Profile array OOB: tx_cduc[]/rx_cddc[] have 2 entries per side but
8T8R hardware CDUC/CDDC numbers go 0-3. Similarly tx_fduc[]/rx_fddc[]
have 4 entries but physical numbers go 0-7. Add fddc_pi/cddc_pi
profile index fields to chan_map, computed once with modular indexing
(% CDUCS_PER_SIDE, % FDUCS_PER_SIDE). This fixes the "Invalid
adi_apollo_cduc_ratio_e enum" error on channels 2-3.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
(cherry picked from commit efac716)
nunojsa
requested review from
CiprianRegus,
amiclaus,
btogorean,
buha,
chegbeli,
danmois,
dbogdan,
machschmitt,
mhennerich and
rbolboac
as code owners
mhennerich
approved these changes
Mar 27, 2026
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PR Description
For some reason, we were missing two commits for ad9088 which was making it to not compile.
PR Type
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