Cavs18

drivers/interrupt_controller/intc_cavs.c

@@ -61,29 +61,29 @@ static void cavs_ictl_isr(const struct device *port)
 				      config->isr_table_offset);
 }
 
-static inline void cavs_ictl_irq_enable(const struct device *dev,
+static void cavs_ictl_irq_enable(const struct device *dev,
 					unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->enable_il = (1 << irq);
+	regs->enable_il = 1 << irq;
 }
 
-static inline void cavs_ictl_irq_disable(const struct device *dev,
+static void cavs_ictl_irq_disable(const struct device *dev,
 					 unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->disable_il = (1 << irq);
+	regs->disable_il = 1 << irq;
 }
 
-static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
+static unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
@@ -94,11 +94,7 @@ static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 	 * corresponding interrupts are disabled. This function
 	 * returns 0 only if ALL the interrupts are disabled.
 	 */
-	if (regs->disable_state_il == 0xFFFFFFFF) {
-		return 0;
-	}
-
-	return 1;
+	return regs->disable_state_il != 0xFFFFFFFF;
 }
 
 static int cavs_ictl_irq_get_line_state(const struct device *dev,
@@ -126,6 +122,11 @@ static const struct irq_next_level_api cavs_apis = {
 #define CAVS_ICTL_INIT(n)						\
 	static int cavs_ictl_##n##_initialize(const struct device *port) \
 	{								\
+		struct cavs_ictl_runtime *context = port->data;		\
+		volatile struct cavs_registers * const regs =		\
+			(struct cavs_registers *)context->base_addr;	\
+		regs->disable_il = ~0;					\
+									\
 		return 0;						\
 	}								\
 									\

samples/audio/sof/prj.conf

@@ -1,3 +1,6 @@
 CONFIG_SOF=y
 CONFIG_SMP=n
 CONFIG_LOG=y
+CONFIG_MP_NUM_CPUS=1
+CONFIG_SYS_HEAP_ALIGNED_ALLOC=y
+CONFIG_DEBUG_MEMORY_USAGE_SCAN=n

soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series

@@ -14,9 +14,6 @@ config SOC
 config SMP
        default y
 
-config MP_NUM_CPUS
-	default 2
-
 config XTENSA_TIMER
 	default n
 
@@ -55,12 +52,6 @@ config TEST_LOGGING_DEFAULTS
 	default n
 	depends on TEST
 
-config IPM_CAVS_IDC
-	default y
-
-config IPM
-       default y
-
 if LOG
 
 config LOG_PRINTK
@@ -79,6 +70,15 @@ endif # LOG
 
 if SMP
 
+config MP_NUM_CPUS
+	default 2
+
+config IPM
+       default y
+
+config IPM_CAVS_IDC
+	default y
+
 config SCHED_IPI_SUPPORTED
 	default y if IPM_CAVS_IDC
 

soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series

@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_18"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -56,7 +65,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -68,12 +77,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 
@@ -83,8 +86,6 @@ config IPM_CAVS_IDC
 config SCHED_IPI_SUPPORTED
 	default y if IPM_CAVS_IDC
 
-endif # SMP
-
 config IPM_INTEL_ADSP
 	default y
 	depends on IPM
@@ -94,4 +95,6 @@ config IPM_CONSOLE
 	depends on CONSOLE
 	depends on IPM
 
+endif # SMP
+
 endif

soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h

@@ -6,8 +6,6 @@
 #ifndef __INC_MEMORY_H
 #define __INC_MEMORY_H
 
-#include <cavs/cpu.h>
-
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE		0x00010000
 
@@ -127,7 +125,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000

soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series

@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_20"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -55,7 +64,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -67,12 +76,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 

soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h

@@ -127,7 +127,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000

soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series

@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_25"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -55,7 +64,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -67,12 +76,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 

soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h

@@ -127,7 +127,7 @@ s/*
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000

soc/xtensa/intel_adsp/common/bootloader/boot_loader.c

@@ -29,6 +29,7 @@ extern void __start(void);
 
 #if NEED_BOOT_LOADER
 #define MANIFEST_SEGMENT_COUNT 3
+#undef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 
 static inline void idelay(int n)
 {
@@ -127,6 +128,7 @@ static void parse_module(struct sof_man_fw_header *hdr,
 #define MAN_SKIP_ENTRIES 1
 #endif
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 static uint32_t get_fw_size_in_use(void)
 {
 	struct sof_man_fw_desc *desc =
@@ -155,6 +157,7 @@ static uint32_t get_fw_size_in_use(void)
 
 	return fw_size_in_use;
 }
+#endif
 
 /* parse FW manifest and copy modules */
 static void parse_manifest(void)
@@ -258,11 +261,13 @@ static uint32_t hp_sram_power_on_memory(uint32_t memory_size)
 	return hp_sram_pm_banks(ebb_in_use);
 }
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
 {
 	/* keep enabled only memory banks used by FW */
 	return hp_sram_power_on_memory(memory_size);
 }
+#endif
 
 static int32_t hp_sram_init(void)
 {
@@ -271,10 +276,12 @@ static int32_t hp_sram_init(void)
 
 #else
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
 {
 	return 0;
 }
+#endif
 
 static uint32_t hp_sram_init(void)
 {
@@ -346,7 +353,9 @@ void boot_master_core(void)
 	/* parse manifest and copy modules */
 	parse_manifest();
 
+#ifdef UNUSED_MEMORY_CALCULATION_HAS_BEEN_FIXED
 	hp_sram_power_off_unused_banks(get_fw_size_in_use());
+#endif
 #endif
 	/* now call SOF entry */
 	__start();

soc/xtensa/intel_adsp/common/include/cavs/cpu.h

@@ -13,10 +13,16 @@
 #ifndef __CAVS_CPU_H__
 #define __CAVS_CPU_H__
 
+#ifndef PLATFORM_CORE_COUNT
 /** \brief Number of available DSP cores (conf. by kconfig) */
+#ifndef CONFIG_SOF
 #define PLATFORM_CORE_COUNT	CONFIG_CORE_COUNT
+#else
+#define PLATFORM_CORE_COUNT	1
+#endif
 
 /** \brief Id of master DSP core */
 #define PLATFORM_MASTER_CORE_ID	0
+#endif
 
 #endif /* __CAVS_CPU_H__ */

soc/xtensa/intel_adsp/common/include/cavs/memory.h

@@ -90,7 +90,6 @@
 /**
  * FIXME check that correct core count is used
  */
-#include <cavs/cpu.h>
 /* SOF Core S configuration */
 #define SRAM_BANK_SIZE		(64 * 1024)
 

soc/xtensa/intel_adsp/common/include/soc.h

@@ -7,6 +7,8 @@
 #include <string.h>
 #include <errno.h>
 
+#include <cavs/version.h>
+
 #include <sys/sys_io.h>
 
 #include <adsp/cache.h>
@@ -61,10 +63,14 @@
 #define SSP_MN_DIV_BASE(x)			\
 	(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
 
-#define PDM_BASE				0x00010000
+#define PDM_BASE				DMIC_BASE
 
 /* SOC DSP SHIM Registers */
+#if CAVS_VERSION == CAVS_VERSION_1_5
 #define SOC_DSP_SHIM_REG_BASE			0x00001000
+#else
+#define SOC_DSP_SHIM_REG_BASE			0x00071f00
+#endif
 
 /* SOC DSP SHIM Register - Clock Control */
 #define SOC_CLKCTL_REQ_AUDIO_PLL_CLK		BIT(31)