Do not hang AXI bus on empty/full queue accesses

Internal-tag: [#74211]

Author: robertszczepanski

src/hci/tti.sv

@@ -74,6 +74,7 @@ module tti
     output logic                   tx_data_queue_reg_rst_o,
     input  logic                   tx_data_queue_reg_rst_we_i,
     input  logic                   tx_data_queue_reg_rst_data_i,
+    input  logic                   tx_data_queue_full_i,
 
     // In-band Interrupt queue
     output logic                    ibi_queue_req_o,
@@ -84,6 +85,8 @@ module tti
     input  logic                    ibi_queue_reg_rst_we_i,
     input  logic                    ibi_queue_reg_rst_data_i,
 
+    input logic bypass_i3c_core_i,
+
     // IBI status
     input logic [1:0] ibi_status_i,
     input logic ibi_status_we_i,
@@ -150,6 +153,15 @@ module tti
     ibi_queue_ready_thld_o = IbiThldWidth'(hwif_tti_i.QUEUE_THLD_CTRL.IBI_THLD.value);
   end : wire_hwif_thld
 
+  logic tx_data_queue_full_r;
+  always_ff @(posedge clk_i or negedge rst_ni) begin : register_fifo_status
+    if (~rst_ni) begin
+      tx_data_queue_full_r <= '0;
+    end else begin
+      tx_data_queue_full_r <= tx_data_queue_full_i;
+    end
+  end
+
   always_comb begin : wire_hwif_xfer
     rx_desc_queue_req_o = hwif_tti_i.RX_DESC_QUEUE_PORT.req;
     hwif_tti_o.RX_DESC_QUEUE_PORT.rd_ack = rx_desc_queue_ack_i;
@@ -169,9 +181,15 @@ module tti
     hwif_tti_o.RESET_CONTROL.RX_DATA_RST.we = rx_data_queue_reg_rst_we_i;
     hwif_tti_o.RESET_CONTROL.RX_DATA_RST.next = rx_data_queue_reg_rst_data_i;
 
-    tx_data_queue_req_o = hwif_tti_i.TX_DATA_PORT.req & hwif_tti_i.TX_DATA_PORT.req_is_wr;
-    tx_data_queue_data_o = hwif_tti_i.TX_DATA_PORT.wr_data;
-    hwif_tti_o.TX_DATA_PORT.wr_ack = tx_data_queue_ack_i;
+    if (bypass_i3c_core_i & tx_data_queue_full_r) begin
+      tx_data_queue_req_o = '0;
+      tx_data_queue_data_o = '0;
+      hwif_tti_o.TX_DATA_PORT.wr_ack = hwif_tti_i.TX_DATA_PORT.req & hwif_tti_i.TX_DATA_PORT.req_is_wr;
+    end else begin
+      tx_data_queue_req_o = hwif_tti_i.TX_DATA_PORT.req & hwif_tti_i.TX_DATA_PORT.req_is_wr;
+      tx_data_queue_data_o = hwif_tti_i.TX_DATA_PORT.wr_data;
+      hwif_tti_o.TX_DATA_PORT.wr_ack = tx_data_queue_ack_i;
+    end
     hwif_tti_o.RESET_CONTROL.TX_DATA_RST.we = tx_data_queue_reg_rst_we_i;
     hwif_tti_o.RESET_CONTROL.TX_DATA_RST.next = tx_data_queue_reg_rst_data_i;
 

src/i3c.sv

@@ -911,6 +911,7 @@ module i3c
   logic                          csr_tti_tx_data_reg_rst;
   logic                          csr_tti_tx_data_reg_rst_we;
   logic                          csr_tti_tx_data_reg_rst_data;
+  logic                          csr_tti_tx_data_full;
 
   // TTI In-band Interrupt (IBI) queue
   logic                          csr_tti_ibi_req;
@@ -979,6 +980,7 @@ module i3c
       .tx_data_queue_reg_rst_o     (csr_tti_tx_data_reg_rst),
       .tx_data_queue_reg_rst_we_i  (csr_tti_tx_data_reg_rst_we),
       .tx_data_queue_reg_rst_data_i(csr_tti_tx_data_reg_rst_data),
+      .tx_data_queue_full_i        (csr_tti_tx_data_full),
 
       // TTI In-band Interrupt (IBI) queue
       .ibi_queue_req_o         (csr_tti_ibi_req),
@@ -989,6 +991,8 @@ module i3c
       .ibi_queue_reg_rst_we_i  (csr_tti_ibi_reg_rst_we),
       .ibi_queue_reg_rst_data_i(csr_tti_ibi_reg_rst_data),
 
+      .bypass_i3c_core_i(bypass_i3c_core),
+
       .recovery_mode_enabled_i(recovery_mode_enabled),
       .ibi_status_i(ibi_status),
       .ibi_status_we_i(ibi_status_we),
@@ -1083,6 +1087,7 @@ module i3c
       .csr_tti_tx_data_queue_reg_rst_i     (csr_tti_tx_data_reg_rst),
       .csr_tti_tx_data_queue_reg_rst_we_o  (csr_tti_tx_data_reg_rst_we),
       .csr_tti_tx_data_queue_reg_rst_data_o(csr_tti_tx_data_reg_rst_data),
+      .csr_tti_tx_data_queue_full_o        (csr_tti_tx_data_full),
 
       // TTI In-band Interrupt (IBI) queue
       .csr_tti_ibi_queue_req_i         (csr_tti_ibi_req),

src/recovery/recovery_executor.sv

@@ -723,9 +723,15 @@ module recovery_executor
 
   // Connect CSR logic to indirect FIFO rx data port
   always_comb begin
-    indirect_rx_rreq_o = hwif_rec_i.INDIRECT_FIFO_DATA.req & !hwif_rec_i.INDIRECT_FIFO_DATA.req_is_wr;
-    hwif_rec_o.INDIRECT_FIFO_DATA.rd_data = indirect_rx_rdata_i;
-    hwif_rec_o.INDIRECT_FIFO_DATA.rd_ack = indirect_rx_rack_i;
+    if (~fifo_empty_r) begin
+      indirect_rx_rreq_o = hwif_rec_i.INDIRECT_FIFO_DATA.req & !hwif_rec_i.INDIRECT_FIFO_DATA.req_is_wr;
+      hwif_rec_o.INDIRECT_FIFO_DATA.rd_data = indirect_rx_rdata_i;
+      hwif_rec_o.INDIRECT_FIFO_DATA.rd_ack = indirect_rx_rack_i;
+    end else begin
+      indirect_rx_rreq_o = '0;
+      hwif_rec_o.INDIRECT_FIFO_DATA.rd_data = '0;
+      hwif_rec_o.INDIRECT_FIFO_DATA.rd_ack = hwif_rec_i.INDIRECT_FIFO_DATA.req & !hwif_rec_i.INDIRECT_FIFO_DATA.req_is_wr;
+    end
   end
 
   // tie unused signals

src/recovery/recovery_handler.sv

@@ -142,6 +142,7 @@ module recovery_handler
     output logic                          csr_tti_rx_data_queue_ready_thld_trig_o,
 
     // TX data queue
+    output logic                          csr_tti_tx_data_queue_full_o,
     input  logic                          csr_tti_tx_data_queue_req_i,
     output logic                          csr_tti_tx_data_queue_ack_o,
     input  logic [      CsrDataWidth-1:0] csr_tti_tx_data_queue_data_i,
@@ -780,7 +781,9 @@ module recovery_handler
   // ......................
   // TX data queue is always connected. The recovery logic does not use it
   logic exec_tti_tx_data_queue_clr;
+  logic indirect_rx_full;
 
+  assign csr_tti_tx_data_queue_full_o = bypass_i3c_core_i ? indirect_rx_full : tti_tx_data_queue_full;
   assign csr_tti_tx_data_queue_ack_o = tti_tx_data_queue_ack;
   assign csr_tti_tx_data_queue_reg_rst_we_o = tti_tx_data_queue_reg_rst_we;
   assign csr_tti_tx_data_queue_reg_rst_data_o = tti_tx_data_queue_reg_rst_next;
@@ -965,7 +968,6 @@ module recovery_handler
 
   logic                          indirect_rx_clr;
 
-  logic                          indirect_rx_full;
   logic                          indirect_rx_empty;
 
   // Indirect FIFO (RX only)

verification/cocotb/top/lib_i3c_top/test_bypass.py

@@ -202,9 +202,7 @@ async def test_indirect_fifo_overflow(dut):
             tb, [random.randint(2, 2**32 - 1)], format="dwords", timeout=100, units="ns"
         )
     except SimTimeoutError:
-        pass
-    else:
-        assert False, "Write to Indirect FIFO was not rejected while it's full!"
+        assert False, "Write to full Indirect FIFO was rejected while it should be ignored"
 
 
 @cocotb.test()
@@ -215,17 +213,18 @@ async def test_indirect_fifo_underflow(dut):
     tb = await initialize(dut)
 
     # Cause the Indirect FIFO to underflow
+    d = 0
     try:
-        await tb.read_csr(
+        d = dword2int(await tb.read_csr(
             tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr,
             4,
             timeout=100,
             units="ns",
-        )
+        ))
     except SimTimeoutError:
-        pass
+        assert False, "Read from empty Indirect FIFO was rejected while it should return 0"
     else:
-        assert False, "Read from empty Indirect FIFO was not rejected!"
+        assert d == 0, "Read from empty Indirect FIFO did not return 0"
 
 
 @cocotb.test()