axi: use awuser and aruser signals for IDs

Signed-off-by: Karol Gugala <[email protected]>

Author: kgugala

src/hci/axi_adapter.sv

@@ -61,7 +61,7 @@ module axi_adapter #(
 
 `ifdef AXI_ID_FILTERING
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i[NumPrivIds],
+    input logic [AxiUserWidth-1:0] priv_ids_i[NumPrivIds],
 `endif
 
     // I3C SW CSR access interface
@@ -123,8 +123,8 @@ module axi_adapter #(
         rsel[j] = '0;
         wsel[j] = '0;
       end else begin
-        rsel[j] = arid_i == priv_ids_i[j];
-        wsel[j] = awid_i == priv_ids_i[j];
+        rsel[j] = aruser_i == priv_ids_i[j];
+        wsel[j] = awuser_i == priv_ids_i[j];
       end
     end
   end

src/i3c.sv

@@ -179,7 +179,7 @@ module i3c
 `ifdef AXI_ID_FILTERING
     // ID Filtering
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds],
+    input logic [AxiUserWidth-1:0] priv_ids_i [NumPrivIds],
 `endif
 `endif
 

src/i3c_wrapper.sv

@@ -99,7 +99,7 @@ module i3c_wrapper #(
 
 `ifdef AXI_ID_FILTERING
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds],
+    input logic [AxiUserWidth-1:0] priv_ids_i [NumPrivIds],
 `endif
 `endif
 

testbench/tb.sv

@@ -89,7 +89,7 @@ logic rst_n;
 
 `ifdef AXI_ID_FILTERING
     logic disable_id_filtering_i;
-    logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds];
+    logic [AxiUserWidth-1:0] priv_ids_i [NumPrivIds];
 `endif
 `endif
 

verification/cocotb/block/axi_adapter_id_filter/test_bus_stress.py

@@ -171,11 +171,11 @@ async def write_read_burst(dut, filter_off=False, awid_priv=True, arid_priv=True
     raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
 
     # Run write burst to fill the FIFO
-    write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, awid=awid)
+    write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, user=awid)
     await with_timeout(write, 1, "us")
 
     # Run read burst to empty the FIFO
-    read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
+    read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, user=arid)
     received_data = await with_timeout(read, 1, "us")
 
     verify_data(test_data, awids, received_data, arids, filter_off, priv_ids)
@@ -210,11 +210,11 @@ async def write_burst_collision_with_read(dut, filter_off=False, awid_priv=True,
     single_write_cycles = 3
 
     async def writer():
-        write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, awid=awid)
+        write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, user=awid)
         await with_timeout(write, 1, "us")
 
     async def reader(return_data):
-        read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
+        read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, user=arid)
         return_data.extend(await with_timeout(read, 1, "us"))
 
     received_data = []
@@ -237,7 +237,7 @@ async def test_write_burst_collision_with_read_id_filter_off(dut):
     await write_burst_collision_with_read(dut, True)
 
 
-@cocotb.test()
+@cocotb.test(skip=False)
 async def test_write_burst_collision_with_read_id_filter_on_priv(dut):
     await write_burst_collision_with_read(dut, False, Access.Priv, Access.Priv)
 
@@ -261,11 +261,11 @@ async def read_burst_collision_with_write(dut, filter_off=False, awid_priv=True,
     single_write_cycles = 3
 
     async def writer():
-        write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, awid=awid)
+        write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, user=awid)
         await with_timeout(write, 1, "us")
 
     async def reader(return_data):
-        read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
+        read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, user=arid)
         return_data.extend(await with_timeout(read, 1, "us"))
 
     received_data1 = []
@@ -338,7 +338,7 @@ async def reader():
             _ = await tb.read_csr(raddr, arid=arids[i])
 
     # Fill fifo halfway to avoid reads when empty
-    await tb.axi_m.write_dwords(waddr, range(64), burst=AxiBurstType.FIXED, awid=priv_ids[0])
+    await tb.axi_m.write_dwords(waddr, range(64), burst=AxiBurstType.FIXED, user=priv_ids[0])
 
     w = cocotb.start_soon(writer())
     r = cocotb.start_soon(reader())
@@ -381,7 +381,7 @@ async def reader():
             _ = await tb.read_csr(raddr, arid=arids[i])
             await RisingEdge(tb.clk)
 
-    await tb.axi_m.write_dwords(waddr, range(64), burst=AxiBurstType.FIXED, awid=priv_ids[0])
+    await tb.axi_m.write_dwords(waddr, range(64), burst=AxiBurstType.FIXED, user=priv_ids[0])
 
     w = cocotb.start_soon(writer())
     r = cocotb.start_soon(reader())

verification/cocotb/block/hci_queues_axi/hci_queues_wrapper.sv

@@ -111,7 +111,7 @@ module hci_queues_wrapper
 
 `ifdef AXI_ID_FILTERING
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds],
+    input logic [AxiUserWidth-1:0] priv_ids_i [NumPrivIds],
 `endif
 
     // HCI queues (FSM side)

verification/cocotb/block/lib_adapter/axi_adapter_wrapper.sv

@@ -71,7 +71,7 @@ module axi_adapter_wrapper
     output logic                  fifo_full_o
 `ifdef AXI_ID_FILTERING,
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds]
+    input logic [AxiUserWidth-1:0] priv_ids_i [NumPrivIds]
 `endif
 );
   // I3C SW CSR access interface

verification/cocotb/common/bus2csr.py

@@ -105,7 +105,6 @@ async def write_csr_field(self, reg_addr, field, data, awid=None) -> None:
         await self.write_csr(reg_addr, int2bytes(value), awid=awid)
 
     async def read_csr_field(self, reg_addr, field, arid=None) -> int:
-        """Read -> modify -> write CSR"""
         value = bytes2int(await self.read_csr(reg_addr, arid=arid))
         value = value & field.mask
         value = value >> field.low
@@ -159,7 +158,7 @@ async def read_csr(
     ) -> List[int]:
         """Send a read request & await the response for 'timeout' in 'units'."""
         if arid:
-            self.dut._log.debug(f"AHB doesn't support transaction IDs, ignoring arid={arid}")
+            self.dut._log.debug(f"AHB doesn't support user id, ignoring arid={arid}")
         self.AHBManager.read(addr, size)
         await with_timeout(self.AHBManager.transfer_done(), timeout, units)
         read = self.AHBManager.get_rsp(addr, self.data_byte_width)
@@ -176,7 +175,7 @@ async def write_csr(
     ) -> None:
         """Send a write request & await transfer to finish for 'timeout' in 'units'."""
         if awid:
-            self.dut._log.debug(f"AHB doesn't support transaction IDs, ignoring awid={awid}")
+            self.dut._log.debug(f"AHB doesn't support user_id, ignoring aw_user={awid}")
         data_len = len(data)
         # Extend bytes to size if there's less than that
         if data_len <= size:
@@ -218,7 +217,10 @@ async def read_csr(
         ret_data_only=True,
     ) -> List[int]:
         """Send a read request & await the response."""
-        resp = await with_timeout(self.axi_m.read(addr, size, arid=arid), timeout, units)
+        if arid is not None:
+            resp = await with_timeout(self.axi_m.read(addr, size, user=arid), timeout, units)
+        else:
+            resp = await with_timeout(self.axi_m.read(addr, size), timeout, units)
         if ret_data_only:
             return resp.data
         return resp
@@ -234,7 +236,10 @@ async def write_csr(
     ) -> None:
         """Send a write request & await transfer to finish."""
         # assert not bytes(data)
-        return await with_timeout(self.axi_m.write(addr, bytes(data), awid=awid), timeout, units)
+        if awid is not None:
+            return await with_timeout(self.axi_m.write(addr, bytes(data), user=awid), timeout, units)
+        else:
+            return await with_timeout(self.axi_m.write(addr, bytes(data)), timeout, units)
 
     def _report_response(self, got, expected, is_read=False):
         op = "read" if is_read else "write"
@@ -259,7 +264,7 @@ async def read_access_monitor(self):
 
             while not (self.dut.rvalid.value and self.dut.rready.value):
                 await RisingEdge(self.dut.aclk)
-            rid = self.dut.rid.value
+            rid = self.dut.aruser.value
             rresp = self.dut.rresp.value
             if filter_off or rid in priv_ids:
                 assert rresp == AxiResp.OKAY, self._report_response(rresp, AxiResp.OKAY, True)
@@ -284,7 +289,7 @@ async def write_access_monitor(self):
 
             while not (self.dut.bvalid.value and self.dut.bready.value):
                 await RisingEdge(self.dut.aclk)
-            bid = self.dut.bid.value
+            bid = self.dut.awuser.value
             bresp = self.dut.bresp.value
 
             if filter_off or bid in priv_ids:

verification/cocotb/top/lib_i3c_top/i3c_test_wrapper.sv

@@ -89,7 +89,7 @@ module i3c_test_wrapper #(
 
 `ifdef AXI_ID_FILTERING
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds],
+    input logic [AxiUserWidth-1:0] priv_ids_i [NumPrivIds],
 `endif
 `endif
     // I3C Target Simulation model