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robertszczepanskikgugala
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Exclude bypass specific register from CSR access test
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2 files changed

+4
-3
lines changed

2 files changed

+4
-3
lines changed

verification/cocotb/top/lib_i3c_top/test_csr_access.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -185,8 +185,9 @@ async def test_ec_tti_csr_access(dut):
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@cocotb.test()
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async def test_ec_soc_mgmt_csr_access(dut):
188+
exceptions = ["REC_INTF_REG_W1C_ACCESS"]
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tb = await initialize(dut)
189-
await run_basic_csr_access(tb, tb.reg_map.I3C_EC.SOCMGMTIF)
190+
await run_basic_csr_access(tb, tb.reg_map.I3C_EC.SOCMGMTIF, exceptions)
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@cocotb.test()

verification/cocotb/top/lib_i3c_top/test_recovery.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -974,7 +974,7 @@ async def test_virtual_read_alternating(dut):
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"""
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# Initialize
977-
i3c_controller, i3c_target, tb, recovery = await initialize(dut)
977+
i3c_controller, i3c_target, tb, recovery = await initialize(dut, timeout=100)
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# set regular device dynamic address
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await i3c_controller.i3c_ccc_write(
@@ -1056,7 +1056,7 @@ async def test_payload_available(dut):
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"""
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# Initialize
1059-
i3c_controller, i3c_target, tb, recovery = await initialize(dut, timeout=200)
1059+
i3c_controller, i3c_target, tb, recovery = await initialize(dut, timeout=400)
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fifo_size = (
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dword2int(

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