Adjust Recovery test to improved register descriptions

Author: robertszczepanski

verification/cocotb/block/bus_tx/test_bus_tx.py

@@ -38,8 +38,8 @@ async def setup_test(dut, timings=None, scl_clk_ratio=SCL_CLK_RATIO):
 
     if timings is None:
         timings = {
-            "t_r":  2,
-            "t_f":  2,
+            "t_r": 2,
+            "t_f": 2,
             "t_su": 5,
             "t_hd": 5,
         }
@@ -73,7 +73,7 @@ async def assert_drive_start(dut, sda_value):
         await RisingEdge(dut.clk_i)
     await ReadOnly()
 
-    t_r  = int(dut.t_r_i.value)
+    t_r = int(dut.t_r_i.value)
     t_su = int(dut.t_su_dat_i.value)
     if (t_r + t_su) == 0:
         # SDA should be driven 1 cycle after SCL negedge
@@ -122,6 +122,7 @@ async def send_bit(dut, value):
         assert dut.tx_idle_o.value == 0
         await RisingEdge(dut.clk_i)
 
+
 async def send_byte(dut, data):
     for i in range(8):
         bit = ((data << i) & 0x80) != 0
@@ -137,15 +138,15 @@ async def test_bit_tx_negedge(dut, value, timings, ratio):
         timings = None
     elif timings == "1":
         timings = {
-            "t_r":  1,
-            "t_f":  1,
+            "t_r": 1,
+            "t_f": 1,
             "t_su": 1,
             "t_hd": 1,
         }
     elif timings == "0":
         timings = {
-            "t_r":  0,
-            "t_f":  0,
+            "t_r": 0,
+            "t_f": 0,
             "t_su": 0,
             "t_hd": 0,
         }

verification/cocotb/block/ctrl_edge_detector/test_edge_detector.py

@@ -7,15 +7,16 @@
 from cocotb.handle import SimHandleBase
 from cocotb.triggers import ClockCycles, RisingEdge
 
+
 async def setup(dut):
     """
     Sets up a base for testing
     """
 
     cocotb.log.setLevel("INFO")
 
-    dut.trigger.value   = 0
-    dut.line.value      = 0
+    dut.trigger.value = 0
+    dut.line.value = 0
 
     clock = Clock(dut.clk_i, 2, units="ns")
     cocotb.start_soon(clock.start())
@@ -65,7 +66,7 @@ async def test_pretrigger_with_delay(dut: SimHandleBase):
     cycles = await count_cycles(clk, dut.detect)
 
     # Check cycle count
-    assert cycles == DELAY+1
+    assert cycles == DELAY + 1
 
 
 @cocotb.test()

verification/cocotb/block/ctrl_i3c_bus_monitor/test_i3c_bus_monitor.py

@@ -6,7 +6,7 @@
 import cocotb
 from cocotb.clock import Clock
 from cocotb.handle import SimHandleBase
-from cocotb.triggers import ClockCycles, RisingEdge, ReadOnly
+from cocotb.triggers import ClockCycles, ReadOnly, RisingEdge
 
 
 async def setup(dut):
@@ -45,6 +45,7 @@ def create_default_controller(dut: SimHandleBase) -> I3cController:
         speed=12.5e6,
     )
 
+
 @cocotb.test()
 async def test_bus_monitor_hdr_exit(dut: SimHandleBase):
     """

verification/cocotb/common/utils.py

@@ -267,6 +267,7 @@ def or_null(d, idx):
 
         byte_idx += 4
 
+
 def format_ibi_data(mdb, data):
     """
     Given MDB and a list of data bytes (can be empty) prepare a sequence of
@@ -309,4 +310,3 @@ async def get_interrupt_status(tb):
         intrs[key] = state
 
     return intrs
-

verification/cocotb/noxfile.py

@@ -43,10 +43,12 @@ def _verify(session, test_group, test_type, test_name, coverage=None, simulator=
             "COCOTB_RESULTS_FILE=" + test.filenames["xml"],
         ]
         if simulator == "verilator":
-            plusargs.extend([
-                "+verilator+rand+reset+2",
-                f"+verilator+seed+{seed}",
-            ])
+            plusargs.extend(
+                [
+                    "+verilator+rand+reset+2",
+                    f"+verilator+seed+{seed}",
+                ]
+            )
         if coverage:
             args.append("COVERAGE_TYPE=" + coverage)
 

verification/cocotb/top/lib_i3c_top/boot.py

@@ -52,7 +52,7 @@ async def common_procedure(tb: I3CTopTestInterface):
     return core_config
 
 
-async def boot_init(tb: I3CTopTestInterface, timings = None):
+async def boot_init(tb: I3CTopTestInterface, timings=None):
     """
     Boot sequence model should match the description in "Boot and Initialization" chapter of the documentation.
 
@@ -65,20 +65,16 @@ async def boot_init(tb: I3CTopTestInterface, timings = None):
     # Timing configuration. When none set all to zeros
     if timings is None:
         timings = {
-            "T_R":  0,
-            "T_F":  0,
+            "T_R": 0,
+            "T_F": 0,
             "T_HD_DAT": 0,
             "T_SU_DAT": 0,
         }
 
-    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_R_REG.base_addr,
-        timings["T_R"])
-    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_F_REG.base_addr,
-        timings["T_F"])
-    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_HD_DAT_REG.base_addr,
-        timings["T_HD_DAT"])
-    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_SU_DAT_REG.base_addr,
-        timings["T_SU_DAT"])
+    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_R_REG.base_addr, timings["T_R"])
+    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_F_REG.base_addr, timings["T_F"])
+    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_HD_DAT_REG.base_addr, timings["T_HD_DAT"])
+    await _write_csr(tb, tb.reg_map.I3C_EC.SOCMGMTIF.T_SU_DAT_REG.base_addr, timings["T_SU_DAT"])
 
     await setup_hci_thresholds(tb)
 
@@ -235,7 +231,7 @@ async def umbrella_stby_init(tb):
     await tb.write_csr_field(
         tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.base_addr,
         tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.VIRT_STATIC_ADDR,
-        0x5b,
+        0x5B,
     )
     await tb.write_csr_field(
         tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.base_addr,

verification/cocotb/top/lib_i3c_top/test_ccc.py

@@ -98,8 +98,12 @@ async def test_ccc_setdasa(dut):
     )
     dynamic_address_reg_addr = tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_DEVICE_ADDR.base_addr
     dynamic_address_reg_value = tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR
-    virtual_dynamic_address_reg_addr = tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.base_addr
-    virtual_dynamic_address_reg_value = tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.VIRT_DYNAMIC_ADDR
+    virtual_dynamic_address_reg_addr = (
+        tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.base_addr
+    )
+    virtual_dynamic_address_reg_value = (
+        tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_VIRT_DEVICE_ADDR.VIRT_DYNAMIC_ADDR
+    )
     dynamic_address_reg_valid = (
         tb.reg_map.I3C_EC.STDBYCTRLMODE.STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR_VALID
     )
@@ -110,14 +114,18 @@ async def test_ccc_setdasa(dut):
     dynamic_address_valid = await tb.read_csr_field(
         dynamic_address_reg_addr, dynamic_address_reg_valid
     )
-    virt_dynamic_address = await tb.read_csr_field(virtual_dynamic_address_reg_addr, virtual_dynamic_address_reg_value)
+    virt_dynamic_address = await tb.read_csr_field(
+        virtual_dynamic_address_reg_addr, virtual_dynamic_address_reg_value
+    )
     virt_dynamic_address_valid = await tb.read_csr_field(
         virtual_dynamic_address_reg_addr, virtual_dynamic_address_reg_valid
     )
     assert dynamic_address == DYNAMIC_ADDR, "Unexpected DYNAMIC ADDRESS read from the CSR"
     assert dynamic_address_valid == 1, "New DYNAMIC ADDRESS is not set as valid"
 
-    assert virt_dynamic_address == VIRT_DYNAMIC_ADDR, "Unexpected VIRT DYNAMIC ADDRESS read from the CSR"
+    assert (
+        virt_dynamic_address == VIRT_DYNAMIC_ADDR
+    ), "Unexpected VIRT DYNAMIC ADDRESS read from the CSR"
     assert virt_dynamic_address_valid == 1, "New VIRT DYNAMIC ADDRESS is not set as valid"
 
 
@@ -220,9 +228,7 @@ async def test_ccc_getmrl(dut):
     i3c_controller, _, tb = await test_setup(dut)
     await ClockCycles(tb.clk, 50)
 
-    responses = await i3c_controller.i3c_ccc_read(
-        ccc=command, addr=TGT_ADR, count=3
-    )
+    responses = await i3c_controller.i3c_ccc_read(ccc=command, addr=TGT_ADR, count=3)
     [mrl_msb, mrl_lsb, ibi_payload_size] = responses[0][1]
 
     mrl = (mrl_msb << 8) | mrl_lsb
@@ -500,9 +506,9 @@ async def test_ccc_direct_multiple_wr(dut):
 
     cccs = [
         (TGT_ADR - 1, (0x00, 0xA0)),
-        (TGT_ADR,     (0x00, 0xA1)),
-        (TGT_ADR,     (0x00, 0xA2)),
-        (TGT_ADR + 2, (0x00, 0xA3)), # TGT_ADR + 1 is set as virtual target static address
+        (TGT_ADR, (0x00, 0xA1)),
+        (TGT_ADR, (0x00, 0xA2)),
+        (TGT_ADR + 2, (0x00, 0xA3)),  # TGT_ADR + 1 is set as virtual target static address
     ]
 
     # Send CCCs
@@ -537,8 +543,9 @@ async def test_ccc_direct_multiple_rd(dut):
     await ClockCycles(tb.clk, 50)
 
     # Set MWL in the target
-    acks = await i3c_controller.i3c_ccc_write(ccc=CCC.DIRECT.SETMWL,
-        directed_data=[(TGT_ADR, (0x00, 0x55))])
+    acks = await i3c_controller.i3c_ccc_write(
+        ccc=CCC.DIRECT.SETMWL, directed_data=[(TGT_ADR, (0x00, 0x55))]
+    )
     if acks != [True]:
         dut._log.error("Initial SETMWL failed")
         assert False
@@ -547,8 +554,7 @@ async def test_ccc_direct_multiple_rd(dut):
 
     # Issue multiple directed GETMWL
     addrs = [TGT_ADR - 1, TGT_ADR, TGT_ADR, TGT_ADR + 2]
-    responses = await i3c_controller.i3c_ccc_read(ccc=CCC.DIRECT.GETMWL,
-        addr=addrs, count=2)
+    responses = await i3c_controller.i3c_ccc_read(ccc=CCC.DIRECT.GETMWL, addr=addrs, count=2)
 
     # Check ACKs
     acks = [r[0] for r in responses]