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verification: testplan: Updated naming convention for tests, removed N.A stages
Signed-off-by: Grzegorz Latosinski <[email protected]>
1 parent 74b264f commit 4766dd8

24 files changed

+133
-217
lines changed

‎verification/testplan/block/bus_monitor.hjson‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,17 @@
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testpoints:
44
[
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{
6-
name: get_status
6+
name: bus_monitor
77
desc:
88
'''
99
Tests operation of the bus_monitor module along with its sub-modules.
1010
Performs a number of I3C transactions between a simulated controller
1111
and a simulated target. Counts start, repeated start and stop events
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reported by bus_monitor. Verifies that the counts match what's expected.
1313
'''
14-
stage: N.A.
1514
tests:
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[
17-
test_get_status
16+
bus_monitor
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]
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tags:
2019
[

‎verification/testplan/block/bus_rx_flow.hjson‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@
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requests, verifies that the module returns correct data sampled
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from the SDA line.
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'''
13-
stage: N.A.
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tests:
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[
16-
test_multiple_bit_reads
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multiple_bit_reads
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]
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tags:
1918
[
@@ -28,10 +27,9 @@
2827
requests, verifies that the module returns correct data sampled
2928
from the SDA line.
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'''
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stage: N.A.
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tests:
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[
34-
test_multiple_byte_reads
32+
multiple_byte_reads
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]
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tags:
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[

‎verification/testplan/block/bus_timers.hjson‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,9 @@
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the signals corresponding to bus states get asserted after the
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required time period.
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'''
14-
stage: N.A.
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tests:
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[
17-
test_get_status
16+
bus_timers
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]
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tags:
2019
[

‎verification/testplan/block/bus_tx.hjson‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,9 @@
99
Requests the bus_tx module to drive SDA right after SCL falling
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edge. Checks if the requested bit value is driven correctly
1111
'''
12-
stage: N.A.
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tests:
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[
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test_bit_tx_negedge
14+
bit_tx_negedge
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]
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tags:
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[
@@ -26,10 +25,9 @@
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Requests the bus_tx module to drive SDA just before SCL rising
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edge. Checks if the requested bit value is driven correctly
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'''
29-
stage: N.A.
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tests:
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[
32-
test_bit_tx_pre_posedge
30+
bit_tx_pre_posedge
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]
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tags:
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[
@@ -43,10 +41,9 @@
4341
Requests the bus_tx module to drive SDA just before SCL falling
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edge. Checks if the requested bit value is driven correctly
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'''
46-
stage: N.A.
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tests:
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[
49-
test_bit_tx_high_level
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bit_tx_high_level
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]
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tags:
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[
@@ -60,10 +57,9 @@
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Requests the bus_tx module to drive SDA when SCL in in stable
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low state. Checks if the requested bit value is driven correctly
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'''
63-
stage: N.A.
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tests:
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[
66-
test_bit_tx_low_level
62+
bit_tx_low_level
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]
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tags:
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[
@@ -78,10 +74,9 @@
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a data byte plus T bit to the I3C bus. For each bit sent checks
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if SDA is driven correctly and bus timings are met.
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'''
81-
stage: N.A.
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tests:
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[
84-
test_byte_tx
79+
byte_tx
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]
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tags:
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[

‎verification/testplan/block/bus_tx_flow.hjson‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,9 @@
99
Requests the bus_tx_flow module to drive SDA right after SCL falling
1010
edge. Checks if the requested bit value is driven correctly
1111
'''
12-
stage: N.A.
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tests:
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[
15-
test_bit_tx_negedge
14+
bit_tx_negedge
1615
]
1716
tags:
1817
[
@@ -26,10 +25,9 @@
2625
Requests the bus_tx_flow module to drive SDA just before SCL rising
2726
edge. Checks if the requested bit value is driven correctly
2827
'''
29-
stage: N.A.
3028
tests:
3129
[
32-
test_bit_tx_pre_posedge
30+
bit_tx_pre_posedge
3331
]
3432
tags:
3533
[
@@ -43,10 +41,9 @@
4341
Requests the bus_tx_flow module to drive SDA just before SCL falling
4442
edge. Checks if the requested bit value is driven correctly
4543
'''
46-
stage: N.A.
4744
tests:
4845
[
49-
test_bit_tx_high_level
46+
bit_tx_high_level
5047
]
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tags:
5249
[
@@ -60,10 +57,9 @@
6057
Requests the bus_tx_flow module to drive SDA when SCL in in stable
6158
low state. Checks if the requested bit value is driven correctly
6259
'''
63-
stage: N.A.
6460
tests:
6561
[
66-
test_bit_tx_low_level
62+
bit_tx_low_level
6763
]
6864
tags:
6965
[
@@ -79,10 +75,9 @@
7975
edges of SCL. Once the transmission finishes compares sampled data
8076
with what was requested to be sent.
8177
'''
82-
stage: N.A.
8378
tests:
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[
85-
test_byte_tx
80+
byte_tx
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]
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tags:
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[

‎verification/testplan/block/ccc.hjson‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,17 @@
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testpoints:
44
[
55
{
6-
name: get_status
6+
name: ccc
77
desc:
88
'''
99
Instucts the ccc module to begin servicing GETSTATUS CCC. Feeds
1010
data bytes and bits to the module via its bus_tx/bus_rx interfaces
1111
to mimick actual I3C transaction. Checks if data bytes received
1212
correspond to correct GETSTATUS CCC response.
1313
'''
14-
stage: N.A.
1514
tests:
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[
17-
test_get_status
16+
ccc
1817
]
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tags:
2019
[

‎verification/testplan/block/csr_sw_access.hjson‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,9 @@
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{
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name: read_hci_version_csr
77
desc: Reads the HCI version CSR and verifies its content
8-
stage: N.A.
98
tests:
109
[
11-
test_read_hci_version_csr
10+
read_hci_version_csr
1211
]
1312
tags:
1413
[
@@ -18,10 +17,9 @@
1817
{
1918
name: read_pio_section_offset
2019
desc: Reads the PIO_SECTION_OFFSET CSR and verifies its content
21-
stage: N.A.
2220
tests:
2321
[
24-
test_read_pio_section_offset
22+
read_pio_section_offset
2523
]
2624
tags:
2725
[
@@ -31,10 +29,9 @@
3129
{
3230
name: write_to_controller_device_addr
3331
desc: "Writes to the CONTROLLER_DEVICE_ADDR CSR and verifies if the write was successful "
34-
stage: N.A.
3532
tests:
3633
[
37-
test_write_to_controller_device_addr
34+
write_to_controller_device_addr
3835
]
3936
tags:
4037
[
@@ -48,10 +45,9 @@
4845
Writes to the HC_CAPABILITIES CSR which is read-only for software
4946
Verifies that the write did not succeed.
5047
'''
51-
stage: N.A.
5248
tests:
5349
[
54-
test_write_should_not_affect_ro_csr
50+
write_should_not_affect_ro_csr
5551
]
5652
tags:
5753
[
@@ -61,10 +57,9 @@
6157
{
6258
name: sequence_csr_read
6359
desc: Performs a sequence of CSR reads. Verifies that each one succeeds
64-
stage: N.A.
6560
tests:
6661
[
67-
test_sequence_csr_read
62+
sequence_csr_read
6863
]
6964
tags:
7065
[
@@ -74,10 +69,9 @@
7469
{
7570
name: sequence_csr_write
7671
desc: Performs a sequence of CSR writes. Verifies that each one succeeds
77-
stage: N.A.
7872
tests:
7973
[
80-
test_sequence_csr_write
74+
sequence_csr_write
8175
]
8276
tags:
8377
[

‎verification/testplan/block/descriptor_rx.hjson‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@
1010
descriptors. The test sends N bytes to the module and verifies
1111
that it emits a valid descriptor with data length set to N.
1212
'''
13-
stage: N.A.
1413
tests:
1514
[
16-
test_descriptor_rx
15+
descriptor_rx
1716
]
1817
tags:
1918
[

‎verification/testplan/block/descriptor_tx.hjson‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,9 @@
1212
amount of data. Verifies that the module accepted the descriptor
1313
and allowed the right amount of data bytes to pass through it.
1414
'''
15-
stage: N.A.
1615
tests:
1716
[
18-
test_descriptor_tx
17+
descriptor_tx
1918
]
2019
tags:
2120
[

‎verification/testplan/block/drivers.hjson‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,17 +3,16 @@
33
testpoints:
44
[
55
{
6-
name: get_status
6+
name: test_drivers
77
desc:
88
'''
99
Tests the I3C PHY module. Loops through all possible states of
1010
SDA/SCL for OD and PP mode. Checks if driven data matches the
1111
bus state.
1212
'''
13-
stage: N.A.
1413
tests:
1514
[
16-
test_get_status
15+
drivers
1716
]
1817
tags:
1918
[

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