testplan: Lint

Fix typos, punctuation.

Signed-off-by: Wiktoria Kuna <[email protected]>

Author: wkkuna

verification/testplan/block/bus_tx.hjson

@@ -7,7 +7,7 @@
       desc:
         '''
         Requests the bus_tx module to drive SDA right after SCL falling
-        edge. Checks if the requested bit value is driven correctly
+        edge. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_negedge"]
       tags: ["bus_tx"]
@@ -17,7 +17,7 @@
       desc:
         '''
         Requests the bus_tx module to drive SDA just before SCL rising
-        edge. Checks if the requested bit value is driven correctly
+        edge. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_pre_posedge"]
       tags: ["bus_tx"]
@@ -27,7 +27,7 @@
       desc:
         '''
         Requests the bus_tx module to drive SDA just before SCL falling
-        edge. Checks if the requested bit value is driven correctly
+        edge. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_high_level"]
       tags: ["bus_tx"]
@@ -37,7 +37,7 @@
       desc:
         '''
         Requests the bus_tx module to drive SDA when SCL in in stable
-        low state. Checks if the requested bit value is driven correctly
+        low state. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_low_level"]
       tags: ["bus_tx"]

verification/testplan/block/bus_tx_flow.hjson

@@ -7,7 +7,7 @@
       desc:
         '''
         Requests the bus_tx_flow module to drive SDA right after SCL falling
-        edge. Checks if the requested bit value is driven correctly
+        edge. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_negedge"]
       tags: ["bus_tx_flow"]
@@ -17,7 +17,7 @@
       desc:
         '''
         Requests the bus_tx_flow module to drive SDA just before SCL rising
-        edge. Checks if the requested bit value is driven correctly
+        edge. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_pre_posedge"]
       tags: ["bus_tx_flow"]
@@ -27,7 +27,7 @@
       desc:
         '''
         Requests the bus_tx_flow module to drive SDA just before SCL falling
-        edge. Checks if the requested bit value is driven correctly
+        edge. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_high_level"]
       tags: ["bus_tx_flow"]
@@ -37,7 +37,7 @@
       desc:
         '''
         Requests the bus_tx_flow module to drive SDA when SCL in in stable
-        low state. Checks if the requested bit value is driven correctly
+        low state. Checks if the requested bit value is driven correctly.
         '''
       tests: ["bit_tx_low_level"]
       tags: ["bus_tx_flow"]

verification/testplan/block/ccc.hjson

@@ -6,9 +6,9 @@
       name: ccc
       desc:
         '''
-        Instucts the ccc module to begin servicing GETSTATUS CCC. Feeds
+        Instructs the ccc module to begin servicing GETSTATUS CCC. Feeds
         data bytes and bits to the module via its bus_tx/bus_rx interfaces
-        to mimick actual I3C transaction. Checks if data bytes received
+        to mimic actual I3C transaction. Checks if data bytes received
         correspond to correct GETSTATUS CCC response.
         '''
       tests: ["ccc"]

verification/testplan/block/csr_sw_access.hjson

@@ -4,41 +4,41 @@
   [
     {
       name: read_hci_version_csr
-      desc: Reads the HCI version CSR and verifies its content
+      desc: Reads the HCI version CSR and verifies its content.
       tests: ["read_hci_version_csr"]
       tags: ["adapter"]
     }
     {
       name: read_pio_section_offset
-      desc: Reads the PIO_SECTION_OFFSET CSR and verifies its content
+      desc: Reads the PIO_SECTION_OFFSET CSR and verifies its content.
       tests: ["read_pio_section_offset"]
       tags: ["adapter"]
     }
     {
       name: write_to_controller_device_addr
-      desc: "Writes to the CONTROLLER_DEVICE_ADDR CSR and verifies if the write was successful "
+      desc: "Writes to the CONTROLLER_DEVICE_ADDR CSR and verifies if the write was successful."
       tests: ["write_to_controller_device_addr"]
       tags: ["adapter"]
     }
     {
       name: write_should_not_affect_ro_csr
       desc:
         '''
-        Writes to the HC_CAPABILITIES CSR which is read-only for software
+        Writes to the HC_CAPABILITIES CSR which is read-only for software.
         Verifies that the write did not succeed.
         '''
       tests: ["write_should_not_affect_ro_csr"]
       tags: ["adapter"]
     }
     {
       name: sequence_csr_read
-      desc: Performs a sequence of CSR reads. Verifies that each one succeeds
+      desc: Performs a sequence of CSR reads. Verifies that each one succeeds.
       tests: ["sequence_csr_read"]
       tags: ["adapter"]
     }
     {
       name: sequence_csr_write
-      desc: Performs a sequence of CSR writes. Verifies that each one succeeds
+      desc: Performs a sequence of CSR writes. Verifies that each one succeeds.
       tests: ["sequence_csr_write"]
       tags: ["adapter"]
     }

verification/testplan/block/hci_queues.hjson

@@ -35,7 +35,7 @@
         Puts 10 data words to the HCI RX data queue. Writes to the
         RESET_CONTROL CSR to the bit responsible for clearing the queue,
         polls the CSR until the bit gets cleared by hardware. Puts and
-        gets another data word from the queue to check if it was cleared
+        gets another data word from the queue to check if it was cleared.
         '''
       tests: ["clear_on_nonempty_rx_queue"]
       tags: ["hci_queues"]
@@ -47,7 +47,7 @@
         Puts 10 data words to the HCI TX data queue. Writes to the
         RESET_CONTROL CSR to the bit responsible for clearing the queue,
         polls the CSR until the bit gets cleared by hardware. Puts and
-        gets another data word from the queue to check if it was cleared
+        gets another data word from the queue to check if it was cleared.
         '''
       tests: ["clear_on_nonempty_tx_queue"]
       tags: ["hci_queues"]
@@ -59,7 +59,7 @@
         Puts 10 data words to the HCI IBI queue. Writes to the
         RESET_CONTROL CSR to the bit responsible for clearing the queue,
         polls the CSR until the bit gets cleared by hardware. Puts and
-        gets another data word from the queue to check if it was cleared
+        gets another data word from the queue to check if it was cleared.
         '''
       tests: ["clear_on_nonempty_ibi_queue"]
       tags: ["hci_queues"]
@@ -69,7 +69,7 @@
       desc:
         '''
         Resets the HCI command queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["cmd_capacity_status"]
       tags: ["hci_queues"]
@@ -79,7 +79,7 @@
       desc:
         '''
         Resets the HCI response queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["resp_capacity_status"]
       tags: ["hci_queues"]
@@ -89,7 +89,7 @@
       desc:
         '''
         Resets the HCI RX queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["rx_capacity_status"]
       tags: ["hci_queues"]
@@ -99,7 +99,7 @@
       desc:
         '''
         Resets the HCI TX queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["tx_capacity_status"]
       tags: ["hci_queues"]
@@ -109,7 +109,7 @@
       desc:
         '''
         Resets the HCI IBI queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["ibi_capacity_status"]
       tags: ["hci_queues"]

verification/testplan/block/i3c_bus_monitor.hjson

@@ -20,7 +20,7 @@
       name: target_reset_detection
       desc:
         '''
-        Issues a target reset patterin to the I3C bus, verifies that the
+        Issues a target reset pattern to the I3C bus, verifies that the
         i3c_bus_monitor correctly report it detected.
         '''
       tests: ["target_reset_detection"]

verification/testplan/block/tti_queues.hjson

@@ -7,7 +7,7 @@
       desc:
         '''
         Resets the TTI TX queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["tti_tx_capacity_status"]
       tags: ["tti_queues"]
@@ -17,7 +17,7 @@
       desc:
         '''
         Resets the TTI TX descriptor queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["tti_tx_desc_capacity_status"]
       tags: ["tti_queues"]
@@ -27,7 +27,7 @@
       desc:
         '''
         Resets the TTI RX queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["tti_rx_capacity_status"]
       tags: ["tti_queues"]
@@ -37,7 +37,7 @@
       desc:
         '''
         Resets the TTI RX descriptor queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["tti_rx_desc_capacity_status"]
       tags: ["tti_queues"]
@@ -173,7 +173,7 @@
       desc:
         '''
         Resets the TTI TX IBI queue and verifies that it is empty
-        afterwards
+        afterwards.
         '''
       tests: ["tti_ibi_capacity_status"]
       tags: ["tti_queues"]

verification/testplan/top/target.hjson

@@ -14,7 +14,7 @@
         the agent.
 
         The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz.
-        The I3C bus clock is set to 12.5 MHz
+        The I3C bus clock is set to 12.5 MHz.
         '''
       tests: ["i3c_target_write"]
       tags: ["top"]
@@ -37,7 +37,7 @@
         Repeats the steps N times.
 
         The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz.
-        The I3C bus clock is set to 12.5 MHz
+        The I3C bus clock is set to 12.5 MHz.
         '''
       tests: ["i3c_target_read"]
       tags: ["top"]
@@ -50,17 +50,17 @@
         controller services the IBI. Checks if the mandatory byte (MDB)
         matches on both sides.
 
-        Reads the LAST_IBI_STATUS fiels of the TTI STATUS CSR. Ensures
+        Reads the LAST_IBI_STATUS fields of the TTI STATUS CSR. Ensures
         that it is equal to 0 (no error).
 
         Writes an IBI descriptor followed by N bytes of data to the TTI
         IBI queue. Waits until the controller services the IBI. Checks if
         the mandatory byte (MDB) and data matches on both sides.
 
-        Repeats the LAST_IBI_STATUS check
+        Repeats the LAST_IBI_STATUS check.
 
         The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz.
-        The I3C bus clock is set to 12.5 MHz
+        The I3C bus clock is set to 12.5 MHz.
         '''
       tests: ["i3c_target_ibi"]
       tags: ["top"]
@@ -69,7 +69,7 @@
       name: i3c_target_ibi_retry
       desc:
         '''
-        Disables ACK-ing IBIs in the I3C controller model, issues an ibi
+        Disables ACK-ing IBIs in the I3C controller model, issues an IBI
         from the target by writing to TTI IBI queue. Waits for a fixed
         time period - sufficiently long for the target to retry sending
         the IBI, reads LAST_IBI_STATUS from the TTI STATUS CSR, check
@@ -81,7 +81,7 @@
         the TTI STATUS CSR, check if it is set to 0 (no error).
 
         The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz.
-        The I3C bus clock is set to 12.5 MHz
+        The I3C bus clock is set to 12.5 MHz.
         '''
       tests: ["i3c_target_ibi_retry"]
       tags: ["top"]
@@ -92,14 +92,14 @@
         '''
         Sets a limit on how many IBI data bytes may be accepted in the
         controller model. Issues an IBI with more data bytes by writing
-        to the TTI IBI queue, checks if the IBI gets serivced correctly,
+        to the TTI IBI queue, checks if the IBI gets serviced correctly,
         compares data.
 
         Issues another IBI with data payload within the set limit, checks
         if it gets serviced correctly, compares data.
 
         The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz.
-        The I3C bus clock is set to 12.5 MHz
+        The I3C bus clock is set to 12.5 MHz.
         '''
       tests: ["i3c_target_ibi_data"]
       tags: ["top"]
@@ -120,7 +120,7 @@
         the data written to TTI TX queue in the beginning of the test.
 
         The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz.
-        The I3C bus clock is set to 12.5 MHz
+        The I3C bus clock is set to 12.5 MHz.
         '''
       tests: ["i3c_target_writes_and_reads"]
       tags: ["top"]

verification/testplan/top/target_ccc.hjson

@@ -110,7 +110,7 @@
       name: ccc_enec_disec_bcast
       desc:
         '''
-        Sends boradcast DISEC CCC and verifies that events are disabled.
+        Sends broadcast DISEC CCC and verifies that events are disabled.
         Then, sends broadcast ENEC CCC and checks that events are enabled.
         '''
       tests: ["ccc_enec_disec_bcast"]
@@ -122,7 +122,7 @@
         '''
         Sends directed SETMWL CCC to the target and verifies that the
         register got correctly set. The check is performed by examining
-        relevant wires in the target DUT
+        relevant wires in the target DUT.
         '''
       tests: ["ccc_setmwl_direct"]
       tags: ["top"]
@@ -133,7 +133,7 @@
         '''
         Sends directed SETMRL CCC to the target and verifies that the
         register got correctly set. The check is performed by examining
-        relevant wires in the target DUT
+        relevant wires in the target DUT.
         '''
       tests: ["ccc_setmrl_direct"]
       tags: ["top"]
@@ -144,7 +144,7 @@
         '''
         Sends broadcast SETMWL CCC and verifies that the
         register got correctly set. The check is performed by examining
-        relevant wires in the target DUT
+        relevant wires in the target DUT.
         '''
       tests: ["ccc_setmwl_bcast"]
       tags: ["top"]
@@ -155,7 +155,7 @@
         '''
         Sends SETMRL CCC and verifies that the
         register got correctly set. The check is performed by examining
-        relevant wires in the target DUT
+        relevant wires in the target DUT.
         '''
       tests: ["ccc_setmrl_bcast"]
       tags: ["top"]

verification/testplan/top/target_interrupts.hjson

@@ -23,7 +23,7 @@
         deasserted, writes data to TTI TX data queue followed by writing
         a descriptor to TTI TX descriptor queue, sends a private read
         over I3C and waits for irq_o assertion. Once the interrupt is
-        asserted clears it by writing 1 to the TX_DESC_STAT fiels of TTI
+        asserted clears it by writing 1 to the TX_DESC_STAT fields of TTI
         INTERRUPT_STATUS csr and ensures that irq_o signal gets deasserted.
         '''
       tests: ["tx_desc_stat"]