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wkkunakgugala
wkkuna
authored and
kgugala
committed
Set 'INDIRECT_FIFO_DATA' sw=r
The writes are executed either via I3C or bypass. Only reads are performed by AXI. Signed-off-by: Wiktoria Kuna <[email protected]>
1 parent f230359 commit 54dc640

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10 files changed

+73
-70
lines changed

10 files changed

+73
-70
lines changed

‎src/csr/I3CCSR.sv‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@ module I3CCSR (
306306
decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_4 = cpuif_req_masked & (cpuif_addr == 12'h160);
307307
decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVED = cpuif_req_masked & (cpuif_addr == 12'h164);
308308
decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA = cpuif_req_masked & (cpuif_addr == 12'h168);
309-
is_external |= cpuif_req_masked & (cpuif_addr == 12'h168);
309+
is_external |= cpuif_req_masked & (cpuif_addr == 12'h168) & !cpuif_req_is_wr;
310310
decoded_reg_strb.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER = cpuif_req_masked & (cpuif_addr == 12'h180);
311311
decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL = cpuif_req_masked & (cpuif_addr == 12'h184);
312312
decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR = cpuif_req_masked & (cpuif_addr == 12'h188);
@@ -6043,10 +6043,8 @@ module I3CCSR (
60436043
end
60446044
assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVED.DATA.value = field_storage.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVED.DATA.value;
60456045

6046-
assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.req = decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA;
6046+
assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.req = !decoded_req_is_wr ? decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA : '0;
60476047
assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.req_is_wr = decoded_req_is_wr;
6048-
assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.wr_data = decoded_wr_data;
6049-
assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.wr_biten = decoded_wr_biten;
60506048
assign hwif_out.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER.CAP_ID.value = 8'h12;
60516049
assign hwif_out.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER.CAP_LENGTH.value = 16'h10;
60526050
// Field: I3CCSR.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.PENDING_RX_NACK
@@ -10057,7 +10055,6 @@ module I3CCSR (
1005710055
wr_ack = '0;
1005810056
wr_ack |= hwif_in.PIOControl.COMMAND_PORT.wr_ack;
1005910057
wr_ack |= hwif_in.PIOControl.TX_DATA_PORT.wr_ack;
10060-
wr_ack |= hwif_in.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.wr_ack;
1006110058
wr_ack |= hwif_in.I3C_EC.TTI.TX_DESC_QUEUE_PORT.wr_ack;
1006210059
wr_ack |= hwif_in.I3C_EC.TTI.TX_DATA_PORT.wr_ack;
1006310060
wr_ack |= hwif_in.I3C_EC.TTI.IBI_PORT.wr_ack;

‎src/csr/I3CCSR_pkg.sv‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -587,7 +587,6 @@ package I3CCSR_pkg;
587587
typedef struct packed{
588588
logic rd_ack;
589589
I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__fields__in_t rd_data;
590-
logic wr_ack;
591590
} I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__in_t;
592591

593592
typedef struct packed{
@@ -2054,15 +2053,9 @@ package I3CCSR_pkg;
20542053
I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_RESERVED__DATA__out_t DATA;
20552054
} I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_RESERVED__out_t;
20562055

2057-
typedef struct packed {
2058-
logic [31:0] DATA;
2059-
} I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__fields__out_t;
2060-
20612056
typedef struct packed{
20622057
logic req;
20632058
logic req_is_wr;
2064-
I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__fields__out_t wr_data;
2065-
I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__fields__out_t wr_biten;
20662059
} I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__out_t;
20672060

20682061
typedef struct packed{

‎src/csr/I3CCSR_uvm.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2674,7 +2674,7 @@ package I3CCSR_uvm;
26742674

26752675
virtual function void build();
26762676
this.DATA = new("DATA");
2677-
this.DATA.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
2677+
this.DATA.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
26782678
if (has_coverage(UVM_CVR_REG_BITS)) begin
26792679
foreach(DATA_bit_cg[bt]) DATA_bit_cg[bt] = new();
26802680
end

‎src/rdl/docs/README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1932,7 +1932,7 @@ Component Memory Space (CMS):</p>
19321932

19331933
|Bits|Identifier|Access|Reset|Name|
19341934
|----|----------|------|-----|----|
1935-
|31:0| DATA | rw | 0x0 | — |
1935+
|31:0| DATA | r | 0x0 | — |
19361936

19371937
## StdbyCtrlMode register file
19381938

‎src/rdl/secure_firmware_recovery_interface.rdl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ regfile SecureFirmwareRecoveryInterfaceRegisters{
680680
name = "INDIRECT_FIFO_DATA";
681681
desc = "Indirect memory access to address space configured in INDIRECT_FIFO_CTRL at the Head Pointer offset.";
682682
field {
683-
sw = rw;
683+
sw = r;
684684
hw = rw;
685685
reset = 32'h0;
686686
} DATA[31:0];

‎src/recovery/recovery_executor.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -726,7 +726,6 @@ module recovery_executor
726726
indirect_rx_rreq_o = hwif_rec_i.INDIRECT_FIFO_DATA.req & !hwif_rec_i.INDIRECT_FIFO_DATA.req_is_wr;
727727
hwif_rec_o.INDIRECT_FIFO_DATA.rd_data = indirect_rx_rdata_i;
728728
hwif_rec_o.INDIRECT_FIFO_DATA.rd_ack = indirect_rx_rack_i;
729-
hwif_rec_o.INDIRECT_FIFO_DATA.wr_ack = '0; // TODO: support writes
730729
end
731730

732731
// tie unused signals

‎verification/cocotb/block/axi_adapter/test_bus_stress.py‎

Lines changed: 20 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -78,12 +78,13 @@ async def initialize(dut, timeout=50):
7878
async def test_collision_with_write(dut):
7979
tb, data_len, test_data = await initialize(dut)
8080

81-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
81+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
82+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
8283

8384
async def writer():
8485
# Write sequence should just write data
8586
for d in test_data:
86-
await tb.write_csr(fifo_addr, int2bytes(d))
87+
await tb.write_csr(waddr, int2bytes(d))
8788
# Wait for read to finish in order to avoid multiple writes per read
8889
await tb.axi_m.wait_read()
8990

@@ -98,7 +99,7 @@ async def reader(return_data):
9899
# Awaiting `awvalid` causes reading simultaneously with write data channel activity
99100
if i < (data_len - read_offset):
100101
await RisingEdge(dut.awvalid)
101-
return_data.append(dword2int(await tb.read_csr(fifo_addr)))
102+
return_data.append(dword2int(await tb.read_csr(raddr)))
102103

103104
received_data = []
104105
w = cocotb.start_soon(writer())
@@ -115,7 +116,8 @@ async def reader(return_data):
115116
async def test_collision_with_read(dut):
116117
tb, data_len, test_data = await initialize(dut)
117118

118-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
119+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
120+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
119121

120122
read_offset = 2
121123

@@ -129,7 +131,7 @@ async def writer():
129131
assert not dut.s_cpuif_req_is_wr.value
130132
# Wait additional cycle to line up write with FIFO read delay
131133
await RisingEdge(tb.clk)
132-
await tb.write_csr(fifo_addr, int2dword(d))
134+
await tb.write_csr(waddr, int2dword(d))
133135

134136
async def reader(return_data):
135137
# Wait until there is data in FIFO
@@ -140,7 +142,7 @@ async def reader(return_data):
140142
for _ in range(data_len):
141143
# Wait for write to finish to avoid multiple reads per write
142144
await tb.axi_m.wait_write()
143-
return_data.append(dword2int(await tb.read_csr(fifo_addr)))
145+
return_data.append(dword2int(await tb.read_csr(raddr)))
144146
await RisingEdge(tb.clk)
145147

146148
received_data = []
@@ -158,13 +160,14 @@ async def reader(return_data):
158160
async def test_write_read_burst(dut):
159161
tb, data_len, test_data = await initialize(dut)
160162

161-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
163+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
164+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
162165

163166
# Run write burst to fill the FIFO
164-
await with_timeout(tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED), 1, "us")
167+
await with_timeout(tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us")
165168

166169
# Run read burst to empty the FIFO
167-
received_data = await with_timeout(tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED), 1, "us")
170+
received_data = await with_timeout(tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us")
168171

169172
assert received_data == test_data, "Received data does not match sent data!"
170173

@@ -175,16 +178,17 @@ async def test_write_read_burst(dut):
175178
async def test_write_burst_collision_with_read(dut):
176179
tb, data_len, test_data = await initialize(dut)
177180

178-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
181+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
182+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
179183

180184
# Time in clock cycles to perform single dword write
181185
single_write_cycles = 3
182186

183187
async def writer():
184-
await with_timeout(tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED), 1, "us")
188+
await with_timeout(tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us")
185189

186190
async def reader(return_data):
187-
return_data.extend(await with_timeout(tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"))
191+
return_data.extend(await with_timeout(tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"))
188192

189193
received_data = []
190194
half_write_timer = ClockCycles(tb.clk, data_len * single_write_cycles // 2)
@@ -207,16 +211,17 @@ async def reader(return_data):
207211
async def test_read_burst_collision_with_write(dut):
208212
tb, data_len, test_data = await initialize(dut)
209213

210-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
214+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
215+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
211216

212217
# Time in clock cycles to perform single dword write
213218
single_write_cycles = 3
214219

215220
async def writer():
216-
await with_timeout(tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED), 1, "us")
221+
await with_timeout(tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us")
217222

218223
async def reader(return_data):
219-
return_data.extend(await with_timeout(tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"))
224+
return_data.extend(await with_timeout(tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"))
220225

221226
received_data1 = []
222227
received_data2 = []

‎verification/cocotb/block/axi_adapter_id_filter/test_bus_stress.py‎

Lines changed: 30 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -42,12 +42,13 @@ async def collision_with_write(dut, filter_off=False, awid_priv=Access.Priv, ari
4242
awids = get_ids(priv_ids, data_len, awid_priv)
4343
arids = get_ids(priv_ids, data_len, arid_priv)
4444

45-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
45+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
46+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
4647

4748
async def writer():
4849
# Write sequence should just write data
4950
for d, awid in zip(test_data, awids):
50-
await tb.write_csr(fifo_addr, int2bytes(d), awid=awid)
51+
await tb.write_csr(waddr, int2bytes(d), awid=awid)
5152
# Wait for read to finish in order to avoid multiple writes per read
5253
await tb.axi_m.wait_read()
5354

@@ -62,7 +63,7 @@ async def reader(return_data):
6263
# Awaiting `awvalid` causes reading simultaneously with write data channel activity
6364
if i < (data_len - read_offset):
6465
await RisingEdge(dut.awvalid)
65-
resp = await tb.read_csr(fifo_addr, arid=arids[i])
66+
resp = await tb.read_csr(raddr, arid=arids[i])
6667
return_data.append(dword2int(resp))
6768

6869
received_data = []
@@ -100,7 +101,8 @@ async def collision_with_read(dut, filter_off=False, awid_priv=True, arid_priv=T
100101
awids = get_ids(priv_ids, data_len, awid_priv)
101102
arids = get_ids(priv_ids, data_len, arid_priv)
102103

103-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
104+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
105+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
104106

105107
read_offset = 2
106108

@@ -115,7 +117,7 @@ async def writer():
115117
assert not dut.s_cpuif_req_is_wr.value
116118
# Wait additional cycle to line up write with FIFO read delay
117119
await RisingEdge(tb.clk)
118-
await tb.write_csr(fifo_addr, int2dword(d), awid=awid)
120+
await tb.write_csr(waddr, int2dword(d), awid=awid)
119121

120122
async def reader(return_data):
121123
# Wait until there is data in FIFO
@@ -126,7 +128,7 @@ async def reader(return_data):
126128
for i in range(data_len):
127129
# Wait for write to finish to avoid multiple reads per write
128130
await tb.axi_m.wait_write()
129-
resp = await tb.read_csr(fifo_addr, arid=arids[i])
131+
resp = await tb.read_csr(raddr, arid=arids[i])
130132
return_data.append(dword2int(resp))
131133
await RisingEdge(tb.clk)
132134

@@ -166,14 +168,15 @@ async def write_read_burst(dut, filter_off=False, awid_priv=True, arid_priv=True
166168
arids = get_ids(priv_ids, 1, arid_priv)
167169
awid, arid = awids[0], arids[0]
168170

169-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
171+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
172+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
170173

171174
# Run write burst to fill the FIFO
172-
write = tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED, awid=awid)
175+
write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, awid=awid)
173176
await with_timeout(write, 1, "us")
174177

175178
# Run read burst to empty the FIFO
176-
read = tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
179+
read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
177180
received_data = await with_timeout(read, 1, "us")
178181

179182
verify_data(test_data, awids, received_data, arids, filter_off, priv_ids)
@@ -201,17 +204,18 @@ async def write_burst_collision_with_read(dut, filter_off=False, awid_priv=True,
201204
arids = get_ids(priv_ids, 1, arid_priv)
202205
awid, arid = awids[0], arids[0]
203206

204-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
207+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
208+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
205209

206210
# Time in clock cycles to perform single dword write
207211
single_write_cycles = 3
208212

209213
async def writer():
210-
write = tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED, awid=awid)
214+
write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, awid=awid)
211215
await with_timeout(write, 1, "us")
212216

213217
async def reader(return_data):
214-
read = tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
218+
read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
215219
return_data.extend(await with_timeout(read, 1, "us"))
216220

217221
received_data = []
@@ -251,17 +255,18 @@ async def read_burst_collision_with_write(dut, filter_off=False, awid_priv=True,
251255
arids = get_ids(priv_ids, 1, arid_priv)
252256
awid, arid = awids[0], arids[0]
253257

254-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
258+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
259+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
255260

256261
# Time in clock cycles to perform single dword write
257262
single_write_cycles = 3
258263

259264
async def writer():
260-
write = tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED, awid=awid)
265+
write = tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED, awid=awid)
261266
await with_timeout(write, 1, "us")
262267

263268
async def reader(return_data):
264-
read = tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
269+
read = tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED, arid=arid)
265270
return_data.extend(await with_timeout(read, 1, "us"))
266271

267272
received_data1 = []
@@ -311,12 +316,13 @@ async def test_collision_with_write_mixed_priv(dut):
311316
awids = get_ids(priv_ids, data_len, Access.Mixed)
312317
arids = get_ids(priv_ids, data_len, Access.Mixed)
313318

314-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
319+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
320+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
315321

316322
async def writer():
317323
# Ensure appropriate response based on ID
318324
for d, awid in zip(test_data, awids):
319-
await tb.write_csr(fifo_addr, int2bytes(d), awid=awid)
325+
await tb.write_csr(waddr, int2bytes(d), awid=awid)
320326
# Wait for read to finish in order to avoid multiple writes per read
321327
await tb.axi_m.wait_read()
322328

@@ -330,10 +336,10 @@ async def reader():
330336
for i in range(data_len):
331337
# Awaiting `awvalid` causes reading simultaneously with write data channel activity
332338
await RisingEdge(dut.awvalid)
333-
_ = await tb.read_csr(fifo_addr, arid=arids[i])
339+
_ = await tb.read_csr(raddr, arid=arids[i])
334340

335341
# Fill fifo halfway to avoid reads when empty
336-
await tb.axi_m.write_dwords(fifo_addr, range(64), burst=AxiBurstType.FIXED, awid=priv_ids[0])
342+
await tb.axi_m.write_dwords(waddr, range(64), burst=AxiBurstType.FIXED, awid=priv_ids[0])
337343

338344
w = cocotb.start_soon(writer())
339345
r = cocotb.start_soon(reader())
@@ -347,7 +353,8 @@ async def test_collision_with_read_mixed_priv(dut):
347353
awids = get_ids(priv_ids, data_len, Access.Mixed)
348354
arids = get_ids(priv_ids, data_len, Access.Mixed)
349355

350-
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
356+
waddr = tb.reg_map.I3C_EC.TTI.TX_DATA_PORT.base_addr
357+
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
351358

352359
read_offset = 2
353360

@@ -361,7 +368,7 @@ async def writer():
361368
assert not dut.s_cpuif_req_is_wr.value
362369
# Wait additional cycle to line up write with FIFO read delay
363370
await RisingEdge(tb.clk)
364-
await tb.write_csr(fifo_addr, int2dword(d), awid=awid)
371+
await tb.write_csr(waddr, int2dword(d), awid=awid)
365372

366373
async def reader():
367374
# Wait until there is data in FIFO
@@ -372,10 +379,10 @@ async def reader():
372379
for i in range(data_len):
373380
# Wait for write to finish to avoid multiple reads per write
374381
await tb.axi_m.wait_write()
375-
_ = await tb.read_csr(fifo_addr, arid=arids[i])
382+
_ = await tb.read_csr(raddr, arid=arids[i])
376383
await RisingEdge(tb.clk)
377384

378-
await tb.axi_m.write_dwords(fifo_addr, range(64), burst=AxiBurstType.FIXED, awid=priv_ids[0])
385+
await tb.axi_m.write_dwords(waddr, range(64), burst=AxiBurstType.FIXED, awid=priv_ids[0])
379386

380387
w = cocotb.start_soon(writer())
381388
r = cocotb.start_soon(reader())

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