LINT: Inferred latches

Signed-off-by: Wiktoria Kuna <[email protected]>

Author: wkkuna

src/ctrl/flow_active.sv

@@ -385,6 +385,8 @@ module flow_active
     dct_wdata_hw_o = '0;
     ibi_queue_wdata_o = '0;
     dct_index_hw_o = '0;
+    resp_data_length_q = '0;
+    resp_queue_wdata_o = '0;
     unique case (state)
       // Idle: Wait for command appearance in the Command Queue
       Idle: begin
@@ -480,7 +482,6 @@ module flow_active
 
         if (resp_queue_wready_i) begin
           resp_queue_wvalid_o = 1'b1;
-          // TODO: Fix inferred latch 'resp_queue_wdata_o'
           resp_queue_wdata_o  = resp_desc;
         end
       end

src/ctrl/flow_standby_i2c.sv

@@ -154,12 +154,16 @@ module flow_standby_i2c
     end
   end : update_transfer_active
 
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : undriven_update_resp_data_length
+    response_fifo_wdata_o.__rsvd23_16 <= '0;
+    // TODO: Implement, controller functionality skipped for now
+    response_fifo_wdata_o.err_status <= i3c_resp_err_status_e'(0);
+    response_fifo_wdata_o.tid <= '0;
+  end
   always_ff @(posedge clk_i or negedge rst_ni) begin : update_resp_data_length
     if (!rst_ni) begin
       response_fifo_wdata_o.data_length <= 0;
-      response_fifo_wdata_o.err_status <= i3c_resp_err_status_e'(0);
-      response_fifo_wdata_o.tid <= '0;
-      response_fifo_wdata_o.__rsvd23_16 <= '0;
     end
     else if (deactivate_transfer) response_fifo_wdata_o.data_length <= transaction_byte_count;
   end : update_resp_data_length