@@ -685,4 +685,30 @@ module i3c_target_fsm #(
685
685
686
686
covprop_valid_addr: cover property (@ (posedge clk_i) ($rose (bus_addr_valid)));
687
687
688
+ covergroup cg_bus_event_fsm_transitions @ (posedge clk_i);
689
+ FsmState : coverpoint state_q {
690
+ bins valid_start_trans =
691
+ (Idle => RxFByte);
692
+ bins valid_rstart_trans =
693
+ (RxPWriteData, TxPReadData, TxPReadTbit, Wait => RxFByte),
694
+ (RxSByte => RxSByteRepeated);
695
+ bins valid_stop_trans =
696
+ (RxFByte, CheckFByte, TxAckFByte, RxSByte, RxSByteRepeated, CheckSByte, TxAckSByte,
697
+ RxPWriteData, RxPWriteTbit, TxPReadData, TxPReadTbit, Wait, DoIBI, DoneIBI, DoCCC,
698
+ DoneCCC, DoHotJoin, DoRstAction, DoHdrExit => Idle);
699
+ }
700
+ BusStartEvent : coverpoint bus_start_det_i {
701
+ bins start_detected = { 1'b1 } ;
702
+ }
703
+ BusRStartEvent : coverpoint bus_rstart_det_i {
704
+ bins rstart_detected = { 1'b1 } ;
705
+ }
706
+ BusStopEvent : coverpoint bus_stop_det_i {
707
+ bins stop_detected = { 1'b1 } ;
708
+ }
709
+
710
+ endgroup : cg_bus_event_fsm_transitions
711
+
712
+ cg_bus_event_fsm_transitions cg_bus_event_fsm_trans = new ();
713
+ `endif
688
714
endmodule : i3c_target_fsm
0 commit comments