docs: Provided links to relevant tests

Signed-off-by: Grzegorz Latosinski <[email protected]>

Author: glatosinski

.github/workflows/build-docs.yml

@@ -26,7 +26,7 @@ jobs:
         run: |
           export I3C_ROOT_DIR="`pwd`"
           pip3 install git+https://github.com/antmicro/testplanner.git
-          make verification-docs
+          REPO_URL="$GITHUB_SERVER_URL/$GITHUB_REPOSITORY/tree/$GITHUB_REF_NAME/" make verification-docs
 
       - name: Build Docs
         run: |

Makefile

@@ -26,6 +26,7 @@ CALIPTRA_ROOT       ?= $(THIRD_PARTY_DIR)/caliptra-rtl## Path: caliptra-rtl repo
 # TODO: Connect to version selection in tools/simulators/
 UVM_DIR             ?= $(VERILATOR_UVM_DIR)/## Select UVM version
 SIMULATOR           ?= verilator## Supported: verilator, dsim, questa, vcs
+REPO_URL            ?= https://github.com/chipsalliance/i3c-core/tree/main/
 
 NUM_PROC            := $$(($$(nproc)-1))
 # Environment variables
@@ -133,9 +134,11 @@ tests-uvm-debug: config ## Run debugging I3C Core UVM tests with nox
 tests-tool: ## Run all tool tests
 	cd $(TOOL_VERIF_DIR) && $(PYTHON) -m nox -k "verify" --no-venv
 
-VERIFICATION_PLANS = $(shell find $(TESTPLAN_DIR) -type f -name "*.hjson" -printf "%P\n")
+BLOCKS_VERIFICATION_PLANS = $(shell find $(TESTPLAN_DIR) -type f -name "*.hjson" ! -name "target*.hjson" -printf "%P\n")
+CORE_VERIFICATION_PLANS = $(shell find $(TESTPLAN_DIR) -type f -name "*target*.hjson" -printf "%P\n")
 verification-docs:
-	cd $(TESTPLAN_DIR) && testplanner $(VERIFICATION_PLANS) -o $(TESTPLAN_DIR)/generated
+	cd $(TESTPLAN_DIR) && testplanner $(BLOCKS_VERIFICATION_PLANS) -o $(TESTPLAN_DIR)/generated/testplans_blocks.md --project-root $(I3C_ROOT_DIR) --testplan-file-map $(TESTPLAN_DIR)/source-maps.yml --source-url-prefix $(REPO_URL)
+	cd $(TESTPLAN_DIR) && testplanner $(CORE_VERIFICATION_PLANS) -o $(TESTPLAN_DIR)/generated/testplans_core.md --project-root $(I3C_ROOT_DIR) --testplan-file-map $(TESTPLAN_DIR)/source-maps.yml --source-url-prefix $(REPO_URL)
 
 #
 # Utilities

docs/source/dv.md

@@ -1,7 +1,7 @@
 # Design verification
 
 This chapter presents the available models and tools which are used for I3C verification.
-The core is verified with [the Cocotb/Verilator + unit tests](https://github.com/chipsalliance/i3c-core/tree/main/verification/cocotb/block) and [the UVM test suite](https://github.com/chipsalliance/i3c-core/tree/main/verification/uvm_i3c).
+The core is verified with [the Cocotb + unit tests](https://github.com/chipsalliance/i3c-core/tree/main/verification/cocotb/block) and [the UVM test suite](https://github.com/chipsalliance/i3c-core/tree/main/verification/uvm_i3c).
 
 There are also non-public tests which utilize Avery I3C VIP framework. The tests include: `private_read`, `private_write` and `recovery` and verify operation of target mode private reads and writes and the secure firmware recovery flow respectively.
 
@@ -20,53 +20,10 @@ Definitions:
 
 ### Testplans for individual blocks
 
-```{include} ../../verification/testplan/generated/bus_monitor.md
-```
-```{include} ../../verification/testplan/generated/bus_rx_flow.md
-```
-```{include} ../../verification/testplan/generated/bus_timers.md
-```
-```{include} ../../verification/testplan/generated/bus_tx_flow.md
-```
-```{include} ../../verification/testplan/generated/bus_tx.md
-```
-```{include} ../../verification/testplan/generated/ccc.md
-```
-```{include} ../../verification/testplan/generated/csr_sw_access.md
-```
-```{include} ../../verification/testplan/generated/descriptor_rx.md
-```
-```{include} ../../verification/testplan/generated/descriptor_tx.md
-```
-```{include} ../../verification/testplan/generated/drivers.md
-```
-```{include} ../../verification/testplan/generated/edge_detector.md
-```
-```{include} ../../verification/testplan/generated/flow_standby_i3c.md
-```
-```{include} ../../verification/testplan/generated/hci_queues.md
-```
-```{include} ../../verification/testplan/generated/tti_queues.md
-```
-```{include} ../../verification/testplan/generated/i3c_bus_monitor.md
-```
-```{include} ../../verification/testplan/generated/pec.md
-```
-```{include} ../../verification/testplan/generated/width_converter_8toN.md
-```
-```{include} ../../verification/testplan/generated/width_converter_Nto8.md
+```{include} ../../verification/testplan/generated/testplans_blocks.md
 ```
 
 ### Testplans for the core
 
-```{include} ../../verification/testplan/generated/target_ccc.md
-```
-```{include} ../../verification/testplan/generated/target_hdr.md
-```
-```{include} ../../verification/testplan/generated/target_interrupts.md
-```
-```{include} ../../verification/testplan/generated/target.md
-```
-```{include} ../../verification/testplan/generated/target_recovery.md
+```{include} ../../verification/testplan/generated/testplans_core.md
 ```
-```{include} ../../verification/testplan/generated/target_reset.md

testplans-template/source/dv.md

@@ -1,7 +1,7 @@
 # Design verification
 
 This chapter presents the available models and tools which are used for I3C verification.
-The core is verified with [the Cocotb/Verilator + unit tests](https://github.com/chipsalliance/i3c-core/tree/main/verification/cocotb/block) and [the UVM test suite](https://github.com/chipsalliance/i3c-core/tree/main/verification/uvm_i3c).
+The core is verified with [the Cocotb + unit tests](https://github.com/chipsalliance/i3c-core/tree/main/verification/cocotb/block) and [the UVM test suite](https://github.com/chipsalliance/i3c-core/tree/main/verification/uvm_i3c).
 
 There are also non-public tests which utilize Avery I3C VIP framework. The tests include: `private_read`, `private_write` and `recovery` and verify operation of target mode private reads and writes and the secure firmware recovery flow respectively.
 
@@ -20,53 +20,10 @@ Definitions:
 
 ### Testplans for individual blocks
 
-```{include} ../../verification/testplan/generated/bus_monitor.md
-```
-```{include} ../../verification/testplan/generated/bus_rx_flow.md
-```
-```{include} ../../verification/testplan/generated/bus_timers.md
-```
-```{include} ../../verification/testplan/generated/bus_tx_flow.md
-```
-```{include} ../../verification/testplan/generated/bus_tx.md
-```
-```{include} ../../verification/testplan/generated/ccc.md
-```
-```{include} ../../verification/testplan/generated/csr_sw_access.md
-```
-```{include} ../../verification/testplan/generated/descriptor_rx.md
-```
-```{include} ../../verification/testplan/generated/descriptor_tx.md
-```
-```{include} ../../verification/testplan/generated/drivers.md
-```
-```{include} ../../verification/testplan/generated/edge_detector.md
-```
-```{include} ../../verification/testplan/generated/flow_standby_i3c.md
-```
-```{include} ../../verification/testplan/generated/hci_queues.md
-```
-```{include} ../../verification/testplan/generated/tti_queues.md
-```
-```{include} ../../verification/testplan/generated/i3c_bus_monitor.md
-```
-```{include} ../../verification/testplan/generated/pec.md
-```
-```{include} ../../verification/testplan/generated/width_converter_8toN.md
-```
-```{include} ../../verification/testplan/generated/width_converter_Nto8.md
+```{include} ../../verification/testplan/generated/testplans_blocks.md
 ```
 
 ### Testplans for the core
 
-```{include} ../../verification/testplan/generated/target_ccc.md
-```
-```{include} ../../verification/testplan/generated/target_hdr.md
-```
-```{include} ../../verification/testplan/generated/target_interrupts.md
-```
-```{include} ../../verification/testplan/generated/target.md
-```
-```{include} ../../verification/testplan/generated/target_recovery.md
+```{include} ../../verification/testplan/generated/testplans_core.md
 ```
-```{include} ../../verification/testplan/generated/target_reset.md

verification/testplan/source-maps.yml

@@ -0,0 +1,24 @@
+testplans:
+  - Recovery mode tests:
+    - verification/cocotb/top/lib_i3c_top/test_recovery.py
+  - Enter and exit HDR mode:
+    - verification/cocotb/top/lib_i3c_top/test_enter_exit_hdr_mode.py
+  - target_interrupts:
+    - verification/cocotb/top/lib_i3c_top/test_interrupts.py
+  - target_peripheral_reset:
+    - verification/cocotb/top/lib_i3c_top/test_target_reset.py
+  - pec:
+    - verification/cocotb/block/recovery_pec/test_pec.py
+  - drivers:
+    - verification/cocotb/block/i3c_phy_io/test_drivers.py
+  - CCC handling:
+    - verification/cocotb/top/lib_i3c_top/test_ccc.py
+  - width_converter_[N8]to[N8]:
+    - verification/cocotb/block/{name}/test_converter.py
+  - Target:
+    - verification/cocotb/top/lib_i3c_top/test_i3c_target.py
+  - .*:
+    - verification/cocotb/block/ctrl_{name}/test_{name}.py
+    - verification/cocotb/block/{name}/test_{name}.py
+    - verification/cocotb/block/lib_adapter/test_{name}.py
+    - verification/cocotb/block/lib_hci_queues/{name}.py