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mtdudekmtdudek
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Modify axi_sub to allow for finer granularity
Modifications, added in this commit, are to allow formimg higher address granularity on the device side. Original code aligned all transfers to AXI data width. However, I3C registers are 32 bit, which requires 32 bit address granularity. This commit also renames axi_sub* modules i3c_axi_sub* in order to prevent name collision with caliptra sources. Signed-off-by: Maciej Dudek <[email protected]>
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7 files changed

+50
-20
lines changed

7 files changed

+50
-20
lines changed

‎src/hci/axi_adapter.sv‎

Lines changed: 30 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,14 @@ module axi_adapter #(
7070
input logic s_cpuif_wr_err
7171
);
7272

73+
localparam LowerAddrBits = $clog2(CsrDataWidth/8);
74+
localparam AxiCSRDataShift = $clog2(AxiDataWidth/CsrDataWidth);
75+
localparam UpperAddrBits = LowerAddrBits + AxiCSRDataShift;
76+
localparam ShiftWidth = $clog2(CsrDataWidth);
77+
7378
axi_if #(
7479
.AW(CsrAddrWidth),
75-
.DW(CsrDataWidth),
80+
.DW(AxiDataWidth),
7681
.UW(AxiDataWidth),
7782
.IW(AxiIdWidth)
7883
) axi (
@@ -131,19 +136,21 @@ module axi_adapter #(
131136
logic cpuif_req_stall;
132137
logic i3c_req_write;
133138
logic i3c_req_last;
134-
logic [CsrDataWidth-1:0] i3c_req_wdata;
139+
logic [AxiDataWidth-1:0] i3c_req_wdata;
140+
logic [AxiDataWidth-1:0] i3c_req_wbiten;
135141
logic [AxiDataWidth/8-1:0] i3c_req_wstrb;
136142
logic [2:0] i3c_req_size;
137143
logic [AxiAddrWidth-1:0] i3c_req_addr;
138-
logic [CsrDataWidth-1:0] i3c_req_rdata;
144+
logic [AxiDataWidth-1:0] i3c_req_rdata;
139145
logic [AxiIdWidth-1:0] i3c_req_id;
140-
logic [CsrDataWidth-1:0] i3c_req_user;
146+
logic [AxiDataWidth-1:0] i3c_req_user;
141147

142148
// Instantiate AXI subordinate to component interface module
143-
axi_sub #(
149+
i3c_axi_sub #(
144150
.AW(CsrAddrWidth),
145-
.DW(CsrDataWidth),
146-
.UW(AxiDataWidth),
151+
.AG($clog2(CsrDataWidth/8)),
152+
.DW(AxiDataWidth),
153+
.UW(AxiUserWidth),
147154
.IW(AxiIdWidth)
148155
) axi_sif_i3c (
149156
.clk (clk_i),
@@ -172,7 +179,7 @@ module axi_adapter #(
172179
genvar i;
173180
for (i = 0; i < AxiDataWidth / 8; i = i + 1) begin : g_replicate_strb_bits
174181
always_comb begin
175-
s_cpuif_wr_biten[i*8+:8] = i3c_req_wstrb[i] ? 8'hFF : 8'h00;
182+
i3c_req_wbiten[i*8+:8] = i3c_req_wstrb[i] ? 8'hFF : 8'h00;
176183
end
177184
end
178185

@@ -186,9 +193,22 @@ module axi_adapter #(
186193
s_cpuif_req = i3c_req_dv & ~i3c_req_hld_ext;
187194
s_cpuif_req_is_wr = i3c_req_write;
188195
s_cpuif_addr = i3c_req_addr[CsrAddrWidth-1:0];
189-
s_cpuif_wr_data = i3c_req_wdata;
190-
i3c_req_rdata = s_cpuif_rd_data;
191196
end
197+
generate
198+
if (AxiDataWidth === CsrDataWidth) begin
199+
assign s_cpuif_wr_biten = i3c_req_wbiten;
200+
assign s_cpuif_wr_data = i3c_req_wdata;
201+
assign i3c_req_rdata = s_cpuif_rd_data;
202+
end else if (AxiDataWidth >= CsrDataWidth) begin
203+
assign s_cpuif_wr_biten = i3c_req_wbiten >> {i3c_req_addr[UpperAddrBits-1:LowerAddrBits],{ShiftWidth{1'b0}}};
204+
assign s_cpuif_wr_data = i3c_req_wdata >> {i3c_req_addr[UpperAddrBits-1:LowerAddrBits],{ShiftWidth{1'b0}}};
205+
assign i3c_req_rdata = s_cpuif_rd_data << {i3c_req_addr[UpperAddrBits-1:LowerAddrBits],{ShiftWidth{1'b0}}};
206+
`ifndef SYNTHESIS
207+
end else begin
208+
$error("No implementation for CSR width > interface width");
209+
`endif
210+
end
211+
endgenerate
192212

193213
always_ff @(posedge clk_i or negedge rst_ni) begin
194214
if (~rst_ni) begin

‎src/i3c_wrapper.sv‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,11 @@ module i3c_wrapper #(
139139
`ifdef I3C_USE_AHB
140140
.AhbDataWidth(AhbDataWidth),
141141
.AhbAddrWidth(AhbAddrWidth),
142+
`elsif I3C_USE_AXI
143+
.AxiDataWidth(AxiDataWidth),
144+
.AxiAddrWidth(AxiAddrWidth),
145+
.AxiUserWidth(AxiUserWidth),
146+
.AxiIdWidth(AxiIdWidth),
142147
`endif
143148
.CsrDataWidth(CsrDataWidth),
144149
.CsrAddrWidth(CsrAddrWidth),

‎src/libs/axi_sub/axi_sub.sv‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,11 +27,12 @@
2727
//
2828
// -------------------------------------------------------------
2929

30-
module axi_sub import axi_pkg::*; #(
30+
module i3c_axi_sub import axi_pkg::*; #(
3131
parameter AW = 32, // Address Width
3232
parameter DW = 32, // Data Width
3333
BC = DW/8, // Byte Count
3434
BW = $clog2(BC), // Byte count Width
35+
parameter AG = $clog2(BC), // Address access granularity
3536
parameter UW = 32, // User Width
3637
parameter IW = 1, // ID Width
3738
ID_NUM = 1 << IW, // Don't override
@@ -101,8 +102,9 @@ module axi_sub import axi_pkg::*; #(
101102
logic w_err;
102103

103104

104-
axi_sub_wr #(
105+
i3c_axi_sub_wr #(
105106
.AW (AW ),
107+
.AG (AG ),
106108
.DW (DW ),
107109
.UW (UW ),
108110
.IW (IW )
@@ -135,8 +137,9 @@ module axi_sub import axi_pkg::*; #(
135137

136138
);
137139

138-
axi_sub_rd #(
140+
i3c_axi_sub_rd #(
139141
.AW(AW),
142+
.AG(AG),
140143
.DW(DW),
141144
.UW(UW),
142145
.IW(IW),
@@ -169,7 +172,7 @@ module axi_sub import axi_pkg::*; #(
169172
.rdata(r_rdata)
170173
);
171174

172-
axi_sub_arb #(
175+
i3c_axi_sub_arb #(
173176
.AW(AW),
174177
.DW(DW),
175178
.UW(UW),

‎src/libs/axi_sub/axi_sub_arb.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
//
2323
// -------------------------------------------------------------
2424

25-
module axi_sub_arb import axi_pkg::*; #(
25+
module i3c_axi_sub_arb import axi_pkg::*; #(
2626
parameter AW = 32, // Address Width
2727
parameter DW = 32, // Data Width
2828
BC = DW/8, // Byte Count

‎src/libs/axi_sub/axi_sub_rd.sv‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,12 @@
2626
//
2727
// -------------------------------------------------------------
2828

29-
module axi_sub_rd import axi_pkg::*; #(
29+
module i3c_axi_sub_rd import axi_pkg::*; #(
3030
parameter AW = 32, // Address Width
3131
parameter DW = 32, // Data Width
3232
BC = DW/8, // Byte Count
3333
BW = $clog2(BC), // Byte count Width
34+
parameter AG = $clog2(BC), // Address access granularity
3435
parameter UW = 32, // User Width
3536
parameter IW = 1, // ID Width
3637
ID_NUM = 1 << IW, // Don't override
@@ -205,7 +206,7 @@ module axi_sub_rd import axi_pkg::*; #(
205206
// Address Calculations //
206207
// --------------------------------------- //
207208
// Force aligned address to component
208-
always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)};
209+
always_comb addr = {txn_ctx.addr[AW-1:AG],AG'(0)};
209210
always_comb user = txn_ctx.user;
210211
always_comb id = txn_ctx.id;
211212
always_comb size = txn_ctx.size;

‎src/libs/axi_sub/axi_sub_wr.sv‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,11 +27,12 @@
2727
//
2828
// -------------------------------------------------------------
2929

30-
module axi_sub_wr import axi_pkg::*; #(
30+
module i3c_axi_sub_wr import axi_pkg::*; #(
3131
parameter AW = 32, // Address Width
3232
parameter DW = 32, // Data Width
3333
BC = DW/8, // Byte Count
3434
BW = $clog2(BC), // Byte count Width
35+
parameter AG = $clog2(BC), // Address access granularity
3536
parameter UW = 32, // User Width
3637
parameter IW = 1, // ID Width
3738
ID_NUM = 1 << IW // Don't override
@@ -251,7 +252,7 @@ module axi_sub_wr import axi_pkg::*; #(
251252
// Address Calculations //
252253
// --------------------------------------- //
253254
// Force aligned address to component
254-
always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)};
255+
always_comb addr = {txn_ctx.addr[AW-1:AG],AG'(0)};
255256
always_comb user = txn_ctx.user;
256257
always_comb id = txn_ctx.id;
257258
always_comb wsize = txn_ctx.size;

‎testbench/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ BUILD_DIR = $(I3C_ROOT_DIR)/testbench/build
66
BUILD_ARGS += +define+DIGITAL_IO_I3C -full64 -sverilog +lint=TFIPC-L
77
BUILD_ARGS += +libext+.sv +libext+.v
88
BUILD_ARGS += $(foreach dir,$(VERILOG_INCLUDE_DIRS),-y $(dir))
9-
BUILD_ARGS += -debug_access+all +memcbk -timescale=1ns/1ps
9+
BUILD_ARGS += -debug_access+all +memcbk -timescale=1ns/1ps -assert svaext
1010

1111
SIM_ARGS += +dumpon
1212
EXTRA_ARGS += +vcs+vcdpluson +vpdfile+dump.vpd +warn=noLINX_KRNL

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