wire up entdaa_ccc module

Author: kgugala

src/ctrl/ccc.sv

@@ -115,6 +115,7 @@ module ccc
     input logic bus_rx_done_i,
     output logic bus_rx_req_bit_o,
     output logic bus_rx_req_byte_o,
+    input logic arbitration_lost_i,
 
     // Addr match interface
     input logic [6:0] target_sta_address_i,
@@ -334,6 +335,29 @@ module ccc
     end
   end
 
+  // Mux TX access between regular CCC and ENTDAA
+  logic entdaa_tx_req_bit;
+  logic entdaa_tx_req_byte;
+  logic entdaa_tx_req_value;
+  logic entdaa_tx_sel_od_pp;
+  logic entdaa_rx_req_bit;
+  logic entdaa_rx_req_byte;
+  logic ccc_tx_req_bit;
+  logic ccc_tx_req_byte;
+  logic ccc_tx_req_value;
+  logic ccc_tx_sel_od_pp;
+  logic ccc_rx_req_bit;
+  logic ccc_rx_req_byte;
+
+  always_comb begin: mux_bus_access
+    bus_tx_req_bit_o = entdaa_o ? entdaa_tx_req_bit : ccc_tx_req_bit;
+    bus_tx_req_byte_o = entdaa_o ? entdaa_tx_req_byte : ccc_tx_req_byte;
+    bus_tx_req_value_o = entdaa_o ? entdaa_tx_req_value : ccc_tx_req_value;
+    bus_tx_sel_od_pp_o = entdaa_o ? entdaa_tx_sel_od_pp : ccc_tx_sel_od_pp;
+    bus_rx_req_bit_o = entdaa_o ? entdaa_rx_req_bit : ccc_rx_req_bit;
+    bus_rx_req_byte_o = entdaa_o ? entdaa_rx_req_byte : ccc_rx_req_byte;
+  end
+
   logic have_defining_byte;
   always_comb begin : defining_byte_ccc
     case (command_code)
@@ -346,7 +370,6 @@ module ccc
     endcase
   end
 
-  // TODO: Handle Bcast CCCs
   typedef enum logic [7:0] {
     Idle,
     WaitCCC,
@@ -364,12 +387,14 @@ module ccc
     TxDataTbit,
     WaitForBusCond,
     WaitForStop,
-    DoneCCC
+    DoneCCC,
+    HandleENTDAA
   } state_e;
 
   state_e state_q, state_d;
 
   assign last_tbit_valid = (state_q == RxTbit || state_q == RxDataTbit) && bus_rx_done_i;
+  assign entdaa_o = (state_q == HandleENTDAA);
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : register_tbit
     if (~rst_ni) begin
@@ -400,6 +425,8 @@ module ccc
 
   logic [7:0] rx_data_count;
 
+  logic entdaa_start, entdaa_done;
+
   always_comb begin : addr_matching
     if (target_dyn_address_valid_i) begin
       is_byte_our_addr = command_addr == target_dyn_address_i;
@@ -461,7 +488,7 @@ module ccc
           if (have_defining_byte) state_d = RxDefByte;
           else begin
             // ENTDAA is special
-            if (command_code == ENTDAA) state_d = HandleENTDAA;
+            if (command_code == `I3C_BCAST_ENTDAA) state_d = HandleENTDAA;
             // broadcast CCCs
             else if (~is_direct_cmd) state_d = RxData;
             // direct CCCs
@@ -470,6 +497,9 @@ module ccc
           end
         end
       end
+      HandleENTDAA: begin
+        if (entdaa_done) state_d = Idle;
+      end
       RxDefByte: begin
         if (bus_rx_done_i) state_d = RxDefByteTbit;
       end
@@ -545,13 +575,13 @@ module ccc
 
 
   always_comb begin : state_outputs
-    bus_rx_req_bit_o = '0;
-    bus_rx_req_byte_o = '0;
+    ccc_rx_req_bit = '0;
+    ccc_rx_req_byte = '0;
 
-    bus_tx_req_byte_o = '0;
-    bus_tx_req_bit_o = '0;
-    bus_tx_req_value_o = '0;
-    bus_tx_sel_od_pp_o = '0;
+    ccc_tx_req_byte = '0;
+    ccc_tx_req_bit = '0;
+    ccc_tx_req_value = '0;
+    ccc_tx_sel_od_pp = '0;
 
     done_fsm_o = '0;
     unique case (state_q)
@@ -562,57 +592,57 @@ module ccc
 
       end
       RxTbit: begin
-        bus_rx_req_bit_o  = '1;
-        bus_rx_req_byte_o = '0;
+        ccc_rx_req_bit  = '1;
+        ccc_rx_req_byte = '0;
       end
       RxDefByte: begin
-        bus_rx_req_bit_o  = '0;
-        bus_rx_req_byte_o = '1;
+        ccc_rx_req_bit  = '0;
+        ccc_rx_req_byte = '1;
       end
       RxDefByteTbit: begin
-        bus_rx_req_bit_o  = '1;
-        bus_rx_req_byte_o = '0;
+        ccc_rx_req_bit  = '1;
+        ccc_rx_req_byte = '0;
       end
       RxByte: begin
-        bus_rx_req_bit_o  = '0;
-        bus_rx_req_byte_o = '1;
-        if (bus_rstart_det_i) bus_rx_req_byte_o = '0;
+        ccc_rx_req_bit  = '0;
+        ccc_rx_req_byte = '1;
+        if (bus_rstart_det_i) ccc_rx_req_byte = '0;
       end
       RxDirectDefByteTbit: begin
-        bus_rx_req_bit_o  = '1;
-        bus_rx_req_byte_o = '0;
+        ccc_rx_req_bit  = '1;
+        ccc_rx_req_byte = '0;
       end
       RxDirectAddr: begin
-        bus_rx_req_bit_o  = '0;
-        bus_rx_req_byte_o = '1;
+        ccc_rx_req_bit  = '0;
+        ccc_rx_req_byte = '1;
       end
       TxDirectAddrAck: begin
-        bus_tx_req_byte_o  = '0;
-        bus_tx_req_bit_o   = '1;
-        bus_tx_req_value_o = {7'h00, ~(is_byte_our_addr | is_byte_rsvd_addr | is_byte_virtual_addr)};
+        ccc_tx_req_byte  = '0;
+        ccc_tx_req_bit   = '1;
+        ccc_tx_req_value = {7'h00, ~(is_byte_our_addr | is_byte_rsvd_addr | is_byte_virtual_addr)};
       end
       RxSubCmdByte: begin
       end
       RxData: begin
-        bus_rx_req_bit_o  = '0;
-        bus_rx_req_byte_o = '1;
-        if (bus_rstart_det_i) bus_rx_req_byte_o = '0;
+        ccc_rx_req_bit  = '0;
+        ccc_rx_req_byte = '1;
+        if (bus_rstart_det_i) ccc_rx_req_byte = '0;
       end
       RxDataTbit: begin
-        bus_rx_req_bit_o  = '1;
-        bus_rx_req_byte_o = '0;
+        ccc_rx_req_bit  = '1;
+        ccc_rx_req_byte = '0;
       end
       TxData: begin
-        bus_tx_req_byte_o  = '1;
-        bus_tx_req_bit_o   = '0;
-        bus_tx_req_value_o = tx_data;
-        bus_tx_sel_od_pp_o = '1;
+        ccc_tx_req_byte  = '1;
+        ccc_tx_req_bit   = '0;
+        ccc_tx_req_value = tx_data;
+        ccc_tx_sel_od_pp = '1;
       end
       TxDataTbit: begin
-        bus_tx_req_byte_o  = '0;
-        bus_tx_req_bit_o   = '1;
-        bus_tx_req_value_o = {7'h00, ~tx_data_done};
-        bus_tx_sel_od_pp_o = '1;
+        ccc_tx_req_byte  = '0;
+        ccc_tx_req_bit   = '1;
+        ccc_tx_req_value = {7'h00, ~tx_data_done};
+        ccc_tx_sel_od_pp = '1;
       end
       DoneCCC: begin
         done_fsm_o = '1;
@@ -947,7 +977,38 @@ module ccc
   assign ent_hdr_5_o = '0;
   assign ent_hdr_6_o = '0;
   assign ent_hdr_7_o = '0;
-  assign set_newda_o = '0;
-  assign newda_o = '0;
 
+
+  ccc_entdaa xccc_entdaa (
+    .clk_i,  // Clock
+    .rst_ni, // Async reset, active low
+    .id_i,
+
+    .start_daa_i(entdaa_start),
+    .done_daa_o(entdaa_done),
+
+    // Bus RX interface
+    .bus_rx_data_i,
+    .bus_rx_done_i,
+    .bus_rx_req_bit_o(entdaa_rx_req_bit),
+    .bus_rx_req_byte_o(entdaa_rx_req_byte),
+
+    // Bus TX interface
+    .bus_tx_done_i,
+    .bus_tx_req_byte_o(entdaa_tx_req_byte),
+    .bus_tx_req_bit_o(entdaa_tx_req_bit),
+    .bus_tx_req_value_o(entdaa_tx_req_value),
+    .bus_tx_sel_od_pp_o(entdaa_tx_sel_od_pp),
+
+    // Bus Monitor interface
+    .bus_rstart_det_i,
+    .bus_stop_det_i,
+
+    // bus access
+    .arbitration_lost_i,
+
+    // addr
+    .address_o(newda_o),
+    .address_valid_o(set_newda_o)
+  );
 endmodule

src/ctrl/ccc_entdaa.sv

@@ -5,21 +5,148 @@ module ccc_entdaa
     input logic clk_i,  // Clock
     input logic rst_ni, // Async reset, active low
     input logic [47:0] id_i,
-    input start_daa,
-    output done_daa
+
+    input logic start_daa_i,
+    output logic done_daa_o,
+
+    // Bus RX interface
+    input logic [7:0] bus_rx_data_i,
+    input logic bus_rx_done_i,
+    output logic bus_rx_req_bit_o,
+    output logic bus_rx_req_byte_o,
+
+    // Bus TX interface
+    input logic bus_tx_done_i,
+    output logic bus_tx_req_byte_o,
+    output logic bus_tx_req_bit_o,
+    output logic [7:0] bus_tx_req_value_o,
+    output logic bus_tx_sel_od_pp_o,
+
+    // Bus Monitor interface
+    input logic bus_rstart_det_i,
+    input logic bus_stop_det_i,
+
+    // bus access
+    input logic arbitration_lost_i,
+
+    // addr
+    output logic [7:0] address_o,
+    output logic address_valid_o
 );
 
 
   typedef enum logic [7:0] {
     Idle,
+    WaitStart,
     ReceiveRsvdByte,
     AckRsvdByte,
+    SendNack,
     SendID,
+    LostArbitration,
     ReceiveAddr,
+    AckAddr,
     Done,
     Error
   } state_e;
 
   state_e state_q, state_d;
+  logic [5:0] id_bit_count;
+  logic reserved_word_det;
+
+  logic parity_ok;
+
+  assign reserved_word_det = (bus_rx_data_i[7:1] == 7'h7e && bus_rx_data_i[0] == 0);
+
+  always_comb begin: state_functions
+    state_d = state_q;
+    unique case (state_q)
+      Idle: begin
+        if (start_daa_i) begin
+          state_d <= WaitStart;
+        end
+      end
+      WaitStart: begin
+        if (bus_rstart_det_i) begin
+          state_d <= ReceiveRsvdByte;
+        end
+      end
+      ReceiveRsvdByte: begin
+        if (bus_rx_done_i) begin
+          if (reserved_word_det) state_d <= AckRsvdByte;
+          else state_d <= SendNack;
+        end
+      end
+      AckRsvdByte: begin
+        state_d <= SendID;
+      end
+      SendNack: begin
+        state_d <= Error;
+      end
+      SendID: begin
+        // our Id was overwritten by some other device
+        if (arbitration_lost_i) begin
+          state_d <= LostArbitration;
+        end
+      end
+      ReceiveAddr: begin
+        if (bus_rx_done_i) begin
+          if (parity_ok) state_d <= AckAddr;
+          else state_d <= SendNack;
+        end
+      end
+      Done: begin
+      end
+      Error: begin
+      // we wait here until we receive Stop
+      end
+      default: begin
+      end
+    endcase
+  end
+
+  always_comb begin : state_outputs
+    bus_rx_req_byte_o = '0;
+
+    bus_tx_req_bit_o = '0;
+    bus_tx_req_value_o = '0;
+    bus_tx_sel_od_pp_o = '0;
+    unique case (state_q)
+      Idle: begin
+      end
+      WaitStart: begin
+      end
+      ReceiveRsvdByte: begin
+        bus_rx_req_byte_o = '1;
+      end
+      AckRsvdByte: begin
+        bus_tx_req_bit_o = '1;
+        bus_tx_req_value_o = '0;
+      end
+      SendNack: begin
+        bus_tx_req_bit_o = '1;
+        bus_tx_req_value_o = '0;
+      end
+      SendID: begin
+      end
+      ReceiveAddr: begin
+        bus_rx_req_byte_o = '1;
+      end
+      Done: begin
+      end
+      Error: begin
+      end
+      default: begin
+      end
+   endcase
+  end
+  // Synchronous state transition
+  always_ff @(posedge clk_i or negedge rst_ni) begin : state_transition
+    if (!rst_ni) begin
+      state_q <= Idle;
+    end else begin
+      if (bus_stop_det_i) state_q <= Done;
+      else state_q <= state_d;
+    end
+  end
 
 endmodule

src/ctrl/controller_standby.sv

@@ -381,7 +381,7 @@ module controller_standby
   ) xcontroller_standby_i3c (
       .clk_i(clk_i),
       .rst_ni(rst_ni),
-      .id_i(id_i)
+      .id_i(id_i),
       .ctrl_bus_i(ctrl_bus_i[1]),
       .ctrl_scl_o(ctrl_scl_o[1]),
       .ctrl_sda_o(ctrl_sda_o[1]),