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We apply implicit conditional I/O (inheritance of I/O predicates from branches) to simplify the logic of ram_mux. In addition, we note that in the current mux logic, we only ever have pending requests for the active channel, so we eliminate an unnecessary state element. While we're here, we also switch to using more explicit names.
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Thanks @ericastor! Appreciate the refactor, will have the team look at this. |
magancarz
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Feb 3, 2026
- Reduce build times, fixing many timeouts - Reduce the size of generated IR by orders of magnitude when there are many states, as with deeply nested loops - Improve QoR 1. Caching of phi conditions in GeneratePhiCondition() reduces the size of the IR considerably. 2. The caching from #1 helps to enable the consolidation of entries added to extra_next_state_values, which ultimately feed into a priority select for the next value of the state element. The XLS back-end does much better with this reduced form, with fewer bits in the priority select, fed by ORs over multiple conditions. PiperOrigin-RevId: 863297433
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We apply implicit conditional I/O (inheritance of I/O predicates from branches) to simplify the logic of ram_mux. In addition, we note that in the current mux logic, we only ever have pending requests for the active channel, so we eliminate an unnecessary state element.
While we're here, we also switch to using more explicit names.